An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security

The hybrid hiding encryption algorithm, as its name implies, embraces concepts from both steganography and cryptography. In this exertion, an improved micro-architecture Field Programmable Gate Array (FPGA) implementation of this algorithm is presented. This design overcomes the observed limitations of a previously-designed micro-architecture. These observed limitations are: no exploitation of the possibility of parallel bit replacement, and the fact that the input plaintext was encrypted serially, which caused a dependency between the throughput and the nature of the used secret key. This dependency can be viewed by some as vulnerability in the security of the implemented micro-architecture. The proposed modified micro-architecture is constructed using five basic modules. These modules are; the message cache, the message alignment module, the key cache, the comparator, and at last the encryption module. In this work, we provide comprehensive simulation and implementation results. These are: the timing diagrams, the post-implementation timing and routing reports, and finally the floor plan. Moreover, a detailed comparison with other FPGA implementations is made available and discussed.

💡 Research Summary

The paper presents an improved FPGA micro‑architecture for the Modified Hybrid Hiding Encryption Algorithm (MHHEA), addressing two major shortcomings of the earlier implementation: serial bit replacement and a throughput that depended on the secret key. The new design consists of five core modules—Message Cache, Message Alignment, Key Cache, Comparator, and Encryption—plus a Linear‑Feedback Shift Register (LFSR) based Random Number Generator that supplies the hiding vector.

The 32‑bit plaintext is split into two 16‑bit registers in the Message Cache. In the Message Alignment stage the data is rotated left by the smaller key value and right by the larger key value plus one; this rotation is performed with multiplexers in a single clock cycle, eliminating the need for costly shifting logic. The Key Cache stores sixteen 3‑bit key pairs (48 bits total) and the Comparator instantly supplies the smaller key to the alignment unit. Each key pair is also scrambled by XOR‑ing with bits from the random hiding vector, which mitigates chosen‑plaintext attacks.

The Encryption module uses simple multiplexers controlled by the scrambled key pair to replace the selected bits in the hiding vector with the corresponding plaintext bits. Because the replacement occurs in parallel, the entire set of bits specified by a key pair is processed in one cycle, and a 16‑bit ciphertext is produced every two clock cycles. A “ready” signal indicates when the output is stable, facilitating handshaking with external communication blocks.

Implemented on a Xilinx Spartan‑II device, the design achieves a functional density (throughput per Configurable Logic Block) that surpasses all compared FPGA implementations except the YAEA algorithm, while delivering an overall throughput on the order of 1 Mbps. The authors also provide detailed simulation waveforms, post‑implementation timing and routing reports, and a floor‑plan layout.

Key contributions include: (1) elimination of key‑dependent throughput, (2) full parallel bit replacement, (3) efficient rotation‑based alignment enabling a compact pipeline, and (4) integration of a maximal‑length LFSR to randomize hiding locations. The paper demonstrates that, with careful hardware‑aware adaptation, a hybrid cryptographic‑steganographic algorithm can achieve both high security flexibility and competitive performance on modest FPGA resources. Limitations such as the relatively short 48‑bit key space and the 16‑bit rotation granularity are acknowledged, suggesting avenues for future work.