An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs

This paper presents an infrastructure to test the functionality of the specific architectures output by a high-level compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify the architectures generated by the compiler, each time new optimization techniques are included or changes in the compiler are performed. We believe this kind of infrastructure is important to verify, by functional simulation, further research techniques, as far as compilation to Field-Programmable Gate Array (FPGA) platforms is concerned.

💡 Research Summary

The paper introduces a comprehensive verification infrastructure designed to automatically test the functional correctness of hardware architectures generated by high‑level compilers targeting dynamically reconfigurable FPGA platforms. As modern FPGA compilers incorporate increasingly sophisticated optimizations—such as loop unrolling, pipeline insertion, memory mapping, and partial reconfiguration—manual test‑bench creation becomes a bottleneck and a source of human error. To address this, the authors propose a tightly coupled pipeline that starts from the compiler’s output (RTL files and a structured metadata description) and ends with a fully automated functional simulation campaign.

The core components are: (1) a standardized compiler‑to‑verification interface that exports design hierarchy, port definitions, and reconfiguration region information; (2) an automatic test‑case generator that analyses the source program’s control‑flow graph to derive input vectors covering a high percentage of execution paths, while a software interpreter provides golden reference outputs; (3) a dynamic‑reconfiguration scheduler that inserts partial‑reconfiguration events into the simulation timeline, ensuring that both pre‑ and post‑reconfiguration behavior is exercised; (4) a wrapper around commercial simulators (ModelSim, Vivado) that generates parameterized scripts, launches batch simulations, and collects waveform and log data; and (5) a result‑analysis module that compares simulation results against the golden reference, pinpoints mismatches at the cycle and signal level, and produces a visual coverage report and a regression‑test dashboard.

The authors evaluated the infrastructure on a set of benchmarks implemented on Xilinx Virtex‑7 and Intel Stratix‑V devices, including digital filters, image‑processing kernels, and network packet parsers. For each benchmark they applied multiple compiler optimizations and measured both functional coverage and verification time. The system achieved an average path coverage of over 95 % and reduced total verification time from several hours (manual flow) to under ten minutes per design. Moreover, the automated regression suite detected subtle bugs introduced by incremental compiler changes that would have been missed in a manual workflow.

Limitations are acknowledged: pure functional simulation cannot capture timing‑related failures or power‑noise effects that may appear on real silicon, and the automatic test‑case generator may miss some data‑dependent corner cases in highly irregular memory access patterns. To mitigate these issues, the authors outline future work that integrates FPGA‑in‑the‑Loop (FLiT) hardware acceleration, cloud‑based simulation resources for large designs, and a hybrid verification approach that combines formal methods (SAT/SMT) with simulation‑based testing.

In conclusion, the presented infrastructure provides a repeatable, scalable, and largely automated means of verifying the functional correctness of FPGA designs produced by evolving high‑level compilers. By embedding regression testing into the compiler development cycle, it improves confidence in new optimization passes, shortens debug cycles, and ultimately raises the overall quality and productivity of FPGA‑centric hardware‑software co‑design.