Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores

Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results on test scheduling for an ITC'02 benchmark SOC that has been augmented with five analog cores.

💡 Research Summary

The paper addresses the growing challenge of testing mixed‑signal System‑on‑Chips (SoCs) that integrate both digital and analog embedded cores. While digital‑only testing has been extensively studied, the inclusion of analog cores dramatically raises test cost, time, and design complexity because traditional approaches treat analog testing as a separate, specialized activity. To overcome this, the authors propose a unified testing methodology based on an “analog wrapper” that encapsulates each analog core and presents a purely digital interface compatible with the existing digital Test Access Mechanism (TAM).

The wrapper consists of a low‑resolution ADC for sampling analog inputs, a DAC for converting digital test vectors back to analog drive signals, control logic to switch between normal operation and test mode, and calibration circuitry to compensate for offset and noise. By inserting this wrapper, an analog core can be exercised using the same digital test vectors and infrastructure that drive digital cores, eliminating the need for a dedicated analog test path.

Because the wrapper adds silicon area and power overhead, the authors develop a two‑stage optimization framework. The first stage, “wrapper optimization,” selects parameters such as ADC/DAC resolution, shared reference lines, and comparator design to minimize area while meeting accuracy requirements. Techniques like resource sharing and time‑multiplexing allow a single ADC/DAC block to serve multiple analog cores sequentially, cutting the wrapper’s footprint by up to 30 %. The second stage, “TAM optimization,” allocates TAM ports and schedules test slots based on each core’s bandwidth and time demands. A cost function C = α·Area + β·Time is defined, where α and β reflect the designer’s emphasis on silicon cost versus test duration.

The two optimizations are combined in a heuristic scheduler. First, feasible wrapper configurations are generated for all analog cores, and the configuration with the lowest area cost is selected. Next, with wrapper parameters fixed, the scheduler performs a conflict‑free TAM port assignment using a modified graph‑coloring algorithm that minimizes port contention. The overall test schedule is then evaluated; if the cost exceeds a threshold, wrapper parameters are iteratively refined.

To validate the concept, the authors implement a transistor‑level analog wrapper in a 0.18 µm CMOS process and simulate it with representative analog cores (e.g., a low‑pass filter and a voltage regulator). The wrapper occupies less than 0.45 mm², consumes under 1.2 mW, and achieves test accuracy within 0.1 % of a dedicated analog test setup, confirming its practicality.

For system‑level evaluation, the methodology is applied to an ITC’02 benchmark SOC augmented with five analog cores. Compared with a baseline digital‑only test schedule, the unified approach reduces total test cycles by roughly 18 % while adding less than 3 % to the overall chip area. By adjusting α and β, designers can prioritize either area savings or test time reduction, demonstrating the flexibility of the cost‑oriented framework.

In summary, the paper introduces a low‑cost, scalable solution for mixed‑signal SOC testing: analog wrappers that translate analog behavior into digital test vectors, coupled with a joint wrapper‑and‑TAM optimization heuristic. The results show substantial reductions in test time and silicon overhead, making unified testing a viable option for future SoCs that increasingly blend digital and analog functionality. Future work may explore high‑resolution wrappers for precision analog blocks and extension to multi‑chip module environments.