A Novel Elliptic curve cryptography Processor using NoC design

In this paper, we propose an elliptic curve key generation processor over GF(2m) and GF(P) with Network-on-Chip (NoC) design scheme based on binary scalar multiplication algorithm. Over the Two last decades, Elliptic Curve Cryptography (ECC) has gained increasing acceptance in the industry and the academic community. This interest is mainly caused by the same level of security with relatively small keys provided by ECC comparing to large key size in Rivest Shamir Adleman (RSA). Parallelism can be utilized in different hierarchy levels as shown in many publications. By using NoC, a new method with the reduced latency of point multiplication (with parallel field arithmetic) is introduced in this paper.

💡 Research Summary

The paper presents a hardware architecture for elliptic curve cryptography (ECC) that leverages a Network‑on‑Chip (NoC) to accelerate point multiplication (ECPM) over both binary fields GF(2^m) and prime fields GF(p). After reviewing the mathematical foundations of ECC—including the Weierstrass equations for both field types, group law for point addition and doubling, and scalar multiplication algorithms—the authors adopt the binary double‑and‑add method as the core algorithm. They note that while the scalar multiplication itself is inherently sequential, the underlying field operations (addition, multiplication, squaring, inversion) can be parallelized. To reduce the costly inversion, projective coordinates are used: Jacobian coordinates for GF(p) and López‑Dahab coordinates for GF(2^m), which require only a single inversion at the end of the scalar multiplication.

The proposed processor is partitioned into twelve functional cores, each implementing a specific arithmetic operation (e.g., multiplication, squaring, addition). These cores are interconnected via a 4 × 3 two‑dimensional mesh NoC. The mesh topology is chosen for its simplicity, low area overhead, and power efficiency. Core placement is optimized: multiplication‑heavy cores occupy the central nodes of the mesh to minimize communication distance, while less demanding cores are placed at the corners. A finite‑state controller orchestrates the sequence of operations—initialization, iterative point doubling/addition, and final affine conversion—while the arithmetic logic unit (ALU) can execute multiple field operations in parallel under controller direction.

The NoC provides packet‑based communication between cores, eliminating the bottlenecks associated with traditional shared‑bus interconnects. By exploiting the NoC’s parallel data paths, the design achieves a substantial reduction in latency for point multiplication compared with prior single‑core or bus‑based ECC processors. The authors also argue that supporting both GF(2^m) and GF(p) makes the architecture flexible enough to handle ECC as well as RSA‑type operations, which are naturally defined over prime fields.

Experimental results (though not detailed in the excerpt) reportedly show that the NoC‑based ECC processor outperforms earlier implementations in both speed and power consumption, confirming that data‑transfer efficiency is a dominant factor in ECC hardware performance. The paper concludes that NoC‑centric designs are a promising direction for low‑power, high‑throughput cryptographic accelerators suitable for embedded platforms such as wireless devices, RFID tags, and smart cards. It also highlights the need for further quantitative analysis of NoC parameters (router latency, buffer sizes, clock frequency) and comparative studies with alternative topologies to fully characterize the trade‑offs.