On the Simulation of Time-Triggered Systems on a Chip with BIP

In this report, we present functional models for software and hardware components of Time-Triggered Systems on a Chip (TTSoC). These are modeled in the asynchronous component based language BIP. We demonstrate the usability of our components for simulation of software which is developed for the TTSoC. Our software comprises services and an application part. Our approach allows us to simulate and validate aspects of the software system at an early stage in the development process and without the need to have the TTSoC hardware at hand.

💡 Research Summary

The paper presents a methodology for modeling and simulating Time‑Triggered Systems on a Chip (TTSoC) using the BIP (Behavior‑Interaction‑Priority) component‑based framework. TTSoC architectures consist of multiple cores (hosts) that communicate over a time‑triggered network on chip (TTNoC). Each host is connected to the network via a Trusted Interface Subsystem (TISS), which buffers messages and enforces slot‑based communication schedules. The authors argue that early‑stage software validation is hampered by the unavailability of hardware prototypes, and that a high‑level, executable model can bridge this gap.

The authors first recap BIP’s three layers. Atomic components are labeled transition systems (LTS) enriched with C/C++ functions, guards, and data variables. Ports expose data and synchronize components. Composite components are built by connecting atomic components with connectors that specify which ports may interact. Connectors distinguish trigger ports (active) from synchron ports (passive), and an interaction is either triggered by a trigger port or is the maximal set of synchron ports. Priorities can be added to resolve nondeterminism among enabled interactions.

To capture TTSoC timing, the model includes a global timer component that emits a tick. This tick is subdivided into three subticks (t1, t2, t3) representing the internal steps needed for a message to travel from a TISS, through one or more switches, to another TISS. The global timer synchronizes all components that need to respect the time‑triggered schedule.

The TTNoC itself is modeled as a mesh of switch components. Each switch contains a routing table and ports for incoming and outgoing messages. The authors illustrate a 2×2 mesh connecting six hosts via four TISS units. The mesh permits parallel, non‑interfering communications in the same time slot, which is a key advantage over bus‑based designs.

TISS components are modeled as atomic BIP components with input and output ports, internal buffers, and slot‑allocation logic. When a host wishes to send a message, it writes the data to the TISS buffer; the TISS then participates in an interaction with the global timer and the appropriate switch during the designated subtick. Conversely, incoming messages are delivered from the TTNoC to the host through the TISS in a symmetric fashion.

A significant contribution is the integration of generated C code from industrial automation toolchains (e.g., IEC 61131‑3 code) into the BIP model. The authors wrap these code fragments as BIP actions attached to transitions, enabling software‑in‑the‑loop testing without any physical hardware. As a case study, they model the control software for a sorting station used in industrial automation. The BIP model reproduces the logical flow of the controller, the periodic sensor readings, actuator commands, and the communication with other nodes over the TTNoC.

The paper situates its work among related modeling approaches such as UML, AADL, SystemC, Ptolemy, and Simulink/Stateflow. While those frameworks often emphasize precise timing analysis, the BIP approach deliberately abstracts timing, focusing instead on causal dependencies and interaction correctness. The authors argue that this abstraction is justified because exact timing parameters are often unknown early in the design process, and hardware specifications may still evolve. Instead, the simulation can be used to discover functional constraints (e.g., required ordering, deadlock‑free interaction patterns) that later guide worst‑case execution time (WCET) analysis and hardware design.

Although the paper does not provide quantitative performance results, it offers a thorough description of the BIP models, the connector definitions, and the priority rules used to enforce deterministic behavior where needed. The modeling steps are presented in sufficient detail that other researchers can replicate the approach for different TTSoC configurations.

In conclusion, the authors demonstrate that BIP can serve as an effective high‑level modeling and simulation platform for TTSoC architectures. By providing executable models of both hardware (timers, switches, TISS) and software (generated C code), the approach enables early validation of functional behavior, reduces dependence on unavailable hardware prototypes, and potentially lowers development costs through early detection of design flaws. This contribution is particularly relevant for safety‑critical domains such as automotive and avionics, where TTSoC designs are increasingly adopted.