AIG Rewriting Using 5-Input Cuts

Rewriting is a common approach to logic optimization based on local transformations. Most commercially available logic synthesis tools include a rewriting engine that may be used multiple times on the same netlist during optimization. This paper presents an And-Inverter graph based rewriting algorithm using 5-input cuts. The best circuits are pre-computed for a subset of NPN classes of 5-variable functions. Cut enumeration and Boolean matching are used to identify replacement candidates. The presented approach is expected to complement existing rewriting approaches which are usually based on 4-input cuts. The experimental results show that, by adding the new rewriting algorithm to ABC synthesis tool, we can further reduce the area of heavily optimized large circuits by 5.57% on average.

💡 Research Summary

The paper introduces a novel rewriting algorithm for And‑Inverter Graphs (AIGs) that operates on 5‑input cuts, extending the capabilities of existing rewriting engines that typically rely on 4‑input cuts. Rewriting, a rule‑based local transformation technique, is widely used in logic synthesis to replace sub‑circuits with functionally equivalent but smaller implementations. While previous work (e.g., the ABC tool’s resyn2 flow) demonstrated the effectiveness of 4‑input cut based rewriting, the authors argue that larger cuts can expose more optimization opportunities, especially in heavily optimized large designs.

The methodology consists of two main phases. In the first phase, the authors generate optimal candidate circuits for a selected subset of NPN‑equivalence classes of 5‑variable Boolean functions. There are 61 612 NPN classes for 5‑input functions; however, only 2 749 of these appear as feasible 5‑input cuts in the IWLS 2005 benchmark suite. From these, 1 185 “practical” classes with at least 20 occurrences are chosen. For each class, a best‑area implementation is synthesized using a forest‑list structure that stores AND and XOR nodes, allowing input complementations. The cost metric is defined as the number of AND nodes plus twice the number of XOR nodes reachable from a given node. The algorithm employs a Boolean matcher to compute canonical forms on‑the‑fly, avoiding the need for a 2³²‑entry lookup table, and stores only the canonical form (or its complement) of each function in a hash map. When the forest grows beyond a preset limit, a reduction step removes nodes not referenced by any stored candidate, keeping memory usage tractable.

In the second phase, the algorithm traverses the target AIG in topological order, enumerates all 5‑input cuts for each node using the classic cut enumeration technique, and applies the Boolean matcher to obtain the canonical truth table and the NPN transformation needed to map a candidate circuit onto the cut. For each cut, the algorithm checks whether a pre‑computed candidate circuit exists that does not increase the overall node count (zero‑cost replacements are also accepted because they can restructure the AIG to enable further improvements). The best replacement, i.e., the one yielding the largest net reduction in node count, is applied by reconnecting the candidate’s leaves to the cut’s fan‑ins and updating reference counts.

Experimental evaluation was performed on the IWLS 2005 benchmarks, each containing more than 5 000 AIG nodes after structural hashing. The authors compared two flows: (a) the standard “resyn2; resyn2” sequence, and (b) “resyn2; rewrite5; resyn2”, where rewrite5 denotes the newly introduced 5‑input cut rewriting pass. The results show an average area reduction of 3.50 % (up to 5.57 % for the most benefitted designs) when the extra rewrite5 step is inserted, at the cost of an average 33 % increase in runtime. This demonstrates that the additional optimization effort yields a worthwhile trade‑off for designs where area is a primary concern.

The paper also discusses limitations and future work. Because only a subset of the 5‑variable NPN classes is covered, some functions cannot be optimized by this method. The dynamic Boolean matching incurs a runtime overhead compared to static table look‑ups, suggesting that further acceleration (e.g., specialized data structures or hardware support) could improve scalability. Extending the approach to cover more NPN classes, or even exploring 6‑input cuts, is identified as a promising direction.

In summary, the authors present a practical and effective enhancement to AIG rewriting by leveraging 5‑input cuts. The technique integrates seamlessly into the ABC synthesis framework, provides measurable area savings on large benchmark circuits, and opens avenues for deeper local optimization beyond the capabilities of existing 4‑input cut based methods.