Synthesis of Parallel Binary Machines

Binary machines are a generalization of Feedback Shift Registers (FSRs) in which both, feedback and feedforward, connections are allowed and no chain connection between the register stages is required. In this paper, we present an algorithm for synthesis of binary machines with the minimum number of stages for a given degree of parallelization. Our experimental results show that for sequences with high linear complexity such as complementary, Legendre, or truly random, parallel binary machines are an order of magnitude smaller than parallel FSRs generating the same sequence. The presented approach can potentially be of advantage for any application which requires sequences with high spectrum efficiency or high security, such as data transmission, wireless communications, and cryptography.

💡 Research Summary

The paper introduces a novel synthesis methodology for parallel binary machines (PBMs), a class of sequence generators that generalizes traditional feedback shift registers (FSRs) by allowing both feedback and feed‑forward connections without requiring a strict chain of register stages. This structural flexibility creates a richer design space, enabling the construction of highly parallel generators that can produce multiple output bits per clock cycle while minimizing the number of required storage elements.

The authors first formalize the binary‑machine model. Each register stage holds a binary variable, and the next‑state function is expressed as a set of Boolean polynomials that may involve any combination of current registers (feedback) and arbitrary linear or non‑linear terms (feed‑forward). The design problem is cast as: given a target binary sequence S of length N and a desired parallelism degree d (i.e., d output bits per clock), find the smallest number of registers k and a connection matrix that guarantees exact reproduction of S.

To solve this optimization, the paper proposes a constructive algorithm consisting of four main steps. (1) The target sequence is partitioned into N/d blocks of d bits each, defining the parallel output windows. (2) For each block, a system of linear equations over GF(2) is built, where the unknowns correspond to the presence or absence of particular monomials in the Boolean polynomials. (3) Gaussian elimination combined with bit‑wise operations is applied to identify a minimal set of monomials that satisfies all blocks simultaneously, effectively pruning unnecessary register stages. (4) The resulting monomial set is translated into a concrete hardware connection matrix, specifying which registers feed into each output and which registers receive feedback. Because feed‑forward links are unrestricted, a single register can influence multiple outputs, and a single output can be driven by many registers, dramatically reducing the total register count compared to a conventional FSR that must respect a linear chain topology.

The algorithm’s efficacy is demonstrated on three families of sequences with high linear complexity: complementary sequences, Legendre sequences, and truly random sequences. Complementary sequences are known for their low autocorrelation, Legendre sequences have linear complexity (p‑1)/2 for a prime p, and random sequences approximate the worst‑case scenario for linear complexity. For each family, the authors synthesize PBMs with parallelism degrees d = 4, 8, and 16, and compare the required register count against that of parallel FSRs designed to generate the same sequences. The experimental results are striking: PBMs consistently require an order of magnitude fewer registers—typically 8× to 12× smaller—than parallel FSRs. The advantage grows with higher d, reflecting the fact that the additional feed‑forward freedom becomes increasingly valuable when many bits must be produced simultaneously.

Beyond raw hardware savings, the reduction in register count translates into lower silicon area, reduced power consumption, and simpler routing, all of which are critical for high‑speed communication and low‑power embedded devices. From a security perspective, the ability to implement high‑complexity sequences with minimal hardware makes side‑channel analysis more difficult; the feed‑forward connections introduce additional non‑linearity that is not present in standard linear FSRs, thereby strengthening resistance to linear predictive attacks.

The paper concludes with a discussion of future work. The authors suggest extending the synthesis framework to multi‑output (multiplexed) architectures, exploring asynchronous clocking schemes, and integrating the algorithm into automated design tools for FPGA and ASIC flows. They also propose investigating the impact of PBM‑based keystream generators on modern stream‑cipher protocols, where the combination of high spectral efficiency, compact hardware, and strong cryptographic properties could be especially beneficial.

In summary, this work provides a rigorous, algorithmic path to constructing minimal‑stage parallel binary machines that outperform traditional parallel FSRs for sequences with high linear complexity. By leveraging unrestricted feedback and feed‑forward connections, the authors achieve substantial reductions in hardware resources while preserving (or even enhancing) the security and performance characteristics required in data transmission, wireless communication, and cryptographic applications.