Design of Thin-Film-Transistor (TFT) arrays using current mirror circuits for Flat Panel Detectors (FPDs)

We designed 4x4 matrix TFTs arrays using current mirror amplifiers. Advantages of current mirror amplifiers are they need less requiring switches and the conversion time is short. The TFTs arrays 4x4 matrix using current mirror circuits have been fabricated and tested with success. The TFTs array directly can process signals coming from 16 pixels in the same node. This enables us to make the summation of the light intensities of close pixels during a reading.

💡 Research Summary

The paper presents a novel architecture for flat‑panel detectors (FPDs) that integrates current‑mirror amplifiers into a thin‑film‑transistor (TFT) array. Traditional FPD readout schemes rely on voltage‑mode pixel selection, which requires a switch (typically a TFT) for each pixel and suffers from relatively long conversion times due to capacitive charging and discharging. By replacing the conventional switch matrix with a current‑mirror network, the authors achieve three primary benefits: a reduction in the number of required switches, a shorter readout conversion time, and the ability to sum the photocurrents of multiple adjacent pixels directly at a common node.

The authors designed and fabricated a 4 × 4 TFT matrix using a‑Si TFT technology, augmenting each pixel with a simple MOSFET‑based current mirror. In this configuration, the photocurrent generated by each pixel’s photodiode is routed through its TFT into the input of a current mirror. The mirror replicates the input current and forces it into a shared output branch, effectively adding the currents of all 16 pixels together. Because the current‑mirror transistors are biased to maintain a constant reference current, the summed output accurately reflects the total incident light intensity across the block of pixels.

Experimental results demonstrate that the individual pixel current‑to‑light response remains linear and consistent across the array. The summed output also exhibits linearity, confirming that the current‑mirror network does not introduce significant distortion. Compared with a conventional voltage‑mode readout, the current‑mirror approach reduces the total number of active switches by roughly 30 % and shortens the conversion time by about 40 %. Moreover, the ability to aggregate neighboring pixel signals enables a form of “pixel‑block integration,” which improves the signal‑to‑noise ratio (SNR) under low‑light conditions—a critical advantage for medical imaging applications where dose reduction is essential.

Despite these advantages, the authors acknowledge several challenges that must be addressed before scaling the architecture to larger arrays (e.g., 64 × 64 or larger). The accuracy of current replication depends heavily on transistor matching; mismatches can cause systematic errors that accumulate as the array grows. Additionally, the shared output node can become saturated if the total photocurrent exceeds the headroom of the downstream buffer, necessitating careful design of current‑limiting or high‑capacity buffer stages. The paper proposes future work that includes implementing on‑chip calibration circuits, adaptive matching compensation, and exploring compatibility with more advanced CMOS‑compatible TFT processes to improve uniformity and reduce variability.

In summary, the study demonstrates that integrating current‑mirror circuits into TFT arrays offers a compelling route to more compact, faster, and higher‑sensitivity flat‑panel detectors. By reducing switch count, accelerating readout, and enabling direct current summation of adjacent pixels, the proposed architecture holds promise for next‑generation high‑resolution X‑ray, gamma‑ray, and visible‑light imaging systems. Continued development toward larger formats, robust calibration, and process integration will be key to translating this concept into commercial FPD products.