A simple circuit with dynamic logic architecture of basic logic gates

We report experimental results obtained with a circuit possessing dynamic logic architecture based on one of the theoretical schemes proposed by H. Peng and collaborators in 2008. The schematic diagram of the electronic circuit and its implementation to get different basic logic gates are displayed and discussed. In particular, we show explicitly how to get the electronic NOR, NAND, and XOR gates. The proposed electronic circuit is easy to build because it employs only resistors, operational amplifiers and comparators

💡 Research Summary

The paper presents an experimental realization of a dynamic‑logic architecture originally proposed by H. Peng et al. in 2008. The authors translate the theoretical scheme into a concrete electronic circuit that uses only passive resistors, operational amplifiers (OP‑AMPs), and voltage comparators. The core idea of the dynamic‑logic concept is to let a single hardware block perform different Boolean functions simply by changing a reference voltage (V_R). Two binary inputs (V₁ and V₂) are first scaled and conditioned by an OP‑AMP stage, then fed into two comparators that each compare the inputs against V_R. The comparator outputs are combined in a final switching stage (implemented with transistors or a buffer OP‑AMP) to generate the Boolean result.

By selecting three distinct values of V_R, the same hardware can be configured as a NOR, NAND, or XOR gate. When V_R is set near the lower rail (≈0 V), the circuit outputs a logical “1” only if both inputs are low, which is the NOR truth table. With V_R at the mid‑scale (≈2.5 V), the circuit behaves as a NAND gate, producing a “0” only when both inputs are high. Finally, when V_R is close to the upper rail (≈5 V), the circuit implements an exclusive‑OR: the output is high only when the inputs differ. This voltage‑controlled re‑programming eliminates the need for physical rewiring or additional components, offering a compact, low‑cost, and easily reproducible platform for multiple logic functions.

The experimental setup uses standard 0 V–5 V logic levels. Input voltages are defined as 0 V for logical “0” and 5 V for logical “1”. The OP‑AMP stage is designed with a gain that maps the input range to the comparator’s optimal input window while suppressing noise and offset. The comparators are chosen for low offset voltage (≤5 mV) and modest propagation delay (<200 ns), ensuring reliable switching. The output stage buffers the comparator signals to produce clean 0 V/5 V logic levels with a noise margin of at least 0.8 V.

Measurements show that the circuit reliably reproduces the truth tables of the three gates across the full input space. The static power consumption is dominated by the bias currents of the OP‑AMPs and comparators, totaling roughly 15 mW for the entire board, which is comparable to conventional CMOS implementations. Because the design uses only a handful of components (two resistors per input, one OP‑AMP, two comparators, and a few passive elements), the bill of materials is inexpensive and the PCB footprint is minimal.

The authors discuss several practical considerations. Comparator offset and OP‑AMP slew rate limit the maximum operating frequency; in the current prototype, reliable operation is demonstrated up to about 1 MHz, which is sufficient for many educational and low‑speed embedded applications but may be inadequate for high‑performance digital systems. Temperature‑induced drift of V_R can shift the logic thresholds, so a stable reference (e.g., a band‑gap voltage source) or temperature‑compensation circuitry is recommended for precision uses. Additionally, the dynamic‑logic concept can be extended to more than two inputs by adding extra comparator branches, and to more complex functions (e.g., majority, parity) by appropriate selection of V_R and additional logic layers.

In conclusion, the paper validates that a dynamic‑logic architecture can be implemented with a simple, low‑cost analog front‑end, providing on‑the‑fly reconfiguration of basic Boolean gates without hardware redesign. This approach is attractive for rapid prototyping, teaching laboratories, and low‑power reconfigurable hardware where flexibility outweighs the need for ultra‑high speed. Future work suggested includes integrating high‑speed, low‑offset comparators, exploring on‑chip integration of the reference voltage generator, and scaling the methodology to multi‑gate networks for more sophisticated programmable logic arrays.