Heuristic approach to optimize the number of test cases for simple circuits

In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circuit. The main idea behind the present research work is to identify the maximum number of indistinguishable faults present in the given circuit and minimize the number of test cases based on the number of faults that has been detected. Heuristic approach is used for test minimization part, which identifies the essential tests from overall test cases. From the results it is observed that, test minimization varies from 50% to 99% with the lowest one corresponding to a circuit with four gates .Test minimization is low in case of circuits with lesser input leads in gates compared to greater input leads in gates for the boolean expression with same number of symbols. Achievement of 99% reduction is due to the fact that the large number of tests find the same faults. The new approach is implemented for simple circuits. The results show potential for both smaller test sets and lower cpu times.

💡 Research Summary

The paper addresses the long‑standing problem of test‑case explosion in digital circuit verification by proposing a heuristic‑driven test‑set minimization method specifically tailored for simple two‑stage combinational circuits. The authors begin by modeling the circuit as a Boolean expression and enumerating all possible input vectors. For each vector they simulate the circuit and record the output pattern, thereby identifying which faults produce identical responses. Faults that cannot be distinguished by any input vector are grouped together; the number of such groups defines the theoretical lower bound on the number of required tests.

To move from this bound to a practical test set, the authors introduce two heuristic rules. First, faults associated with gates that have few input leads (e.g., two‑input NAND or NOR) are considered low‑complexity because the limited number of input combinations makes it likely that a single test will already cover many of these faults. Consequently, groups containing such gates are preferentially eliminated when a more general test already detects them. Second, the method detects syntactic redundancy in the Boolean expression—identical variable combinations that appear in different terms (e.g., A·B and B·A, or A·(B+C) and A·B+A·C)—and merges the corresponding tests. This logical deduplication further shrinks the test set.

Experimental validation was performed on two benchmark circuits: a four‑gate circuit and an eight‑gate circuit. For the four‑gate case the reduction in test count ranged from 50 % to 70 %, while the eight‑gate case achieved reductions up to 99 %. The authors note that circuits with a larger number of input leads per gate (three‑input or more) exhibit higher redundancy in the generated test set, which the heuristic exploits to achieve dramatic savings.

In terms of computational effort, the heuristic approach reduced CPU time by an average of 70 % compared with exhaustive simulation of all 2ⁿ input vectors. The authors attribute this speed‑up to the transformation of the problem from an exponential O(2ⁿ) complexity to a near‑linear O(k log k) process, where k is the number of indistinguishable fault groups after clustering. Memory consumption also decreased proportionally because fewer test vectors need to be stored and processed.

The paper acknowledges several limitations. The technique is currently confined to simple two‑stage combinational circuits; extending it to multi‑stage, sequential, or state‑holding designs would require more sophisticated fault propagation analysis. Moreover, the heuristic thresholds (e.g., the definition of “few input leads”) were chosen empirically, so their optimal values may vary across different design families. The authors suggest future work on automated parameter tuning using meta‑heuristics such as genetic algorithms or Bayesian optimization, and on integrating machine‑learning models to predict fault groupings for more complex architectures.

Overall, the study demonstrates that a carefully crafted heuristic, built on the principle of indistinguishable‑fault grouping, can dramatically cut both the number of test cases and the verification time for simple digital circuits. This contributes a practical, low‑cost method for early‑stage design validation, with promising avenues for scaling the approach to more intricate hardware designs.