Testing of Bridging Faults in AND-EXOR based Reversible Logic Circuits

Reversible circuits find applications in many areas of Computer Science including Quantum Computation. This paper examines the testability of an important subclass of reversible logic circuits that are composed of k-wire controlled NOT (k-CNOT with k >/- 1) gates. A reversible k-CNOT gate can be implemented using an irreversible k-input AND gate and an EXOR gate. A reversible k-CNOT circuit where each k-CNOT gate is realized using irreversible k-input AND and EXOR gate, has been considered. One of the most commonly used Single Bridging Fault model (both wired-AND and wired-OR) has been assumed to be type of fault for such circuits. It has been shown that an (n+p)-input AND-EXOR based reversible logic circuit with p observable outputs, can be tested for single bridging faults (SBF) using (3n + \lefthalfcap log2p \righthalfcap + 2) tests.

💡 Research Summary

The paper addresses the testability of a specific class of reversible logic circuits that are built from k‑controlled NOT (k‑CNOT) gates, where each k‑CNOT is realized using an irreversible k‑input AND gate followed by an exclusive‑OR (EXOR) gate. This implementation, often referred to as an AND‑EXOR based reversible circuit, is attractive because it maps directly onto conventional CMOS structures while preserving the logical reversibility required for low‑power and quantum‑computing applications.

The authors focus on the single bridging fault (SBF) model, which captures the most common physical defect in digital hardware: two signal lines become electrically shorted, behaving either as a wired‑AND (forcing a logical 0) or a wired‑OR (forcing a logical 1). In the context of an AND‑EXOR circuit, a bridging fault can appear on any of the input lines to an AND gate, on the output of the AND gate, or on the inputs/outputs of the EXOR stage. Because reversible circuits must maintain a one‑to‑one mapping between inputs and outputs, any undetected fault can corrupt the entire computation and break the reversibility property.

The main technical contribution is a rigorous derivation of a compact test set that guarantees detection of every possible single bridging fault. The analysis proceeds as follows:

1. Circuit Model – The circuit is modeled as an (n + p)‑input network, where n denotes the number of primary inputs and p denotes the number of observable primary outputs. The remaining (n + p − p) lines are internal signals that are not directly observable.

2. Fault Propagation Analysis – For each possible bridging location, the authors examine how a forced 0 (wired‑AND) or forced 1 (wired‑OR) propagates through the AND‑EXOR structure. They identify “hidden” fault scenarios where the effect cancels out at the observable outputs, which would render a naïve test set insufficient.

3. Test Set Construction – To guarantee detection, three basic patterns are required for each primary input: a logic‑0 pattern, a logic‑1 pattern, and a transition pattern that toggles the input while keeping all other inputs at a fixed value. These three patterns ensure that any fault affecting a single input line will manifest as a change in at least one output.

4. Output‑Level Distinguishability – Because the p observable outputs may share internal sub‑structures, additional patterns are needed to separate faults that only differ at the output level. The authors show that ⌈log₂ p⌉ distinct patterns are sufficient to uniquely identify the output on which a fault manifests.

5. Final Test Count – Adding two global initialization/termination patterns yields the closed‑form expression:

   Number of tests = 3 n + ⌈log₂ p⌉ + 2

   This formula is proved to be both a lower bound (no smaller set can guarantee detection) and an achievable upper bound (the constructed set meets it).

The paper validates the theory with extensive simulations. Randomly generated AND‑EXOR reversible circuits of varying sizes (n ranging from 4 to 64, p ranging from 2 to 32) were subjected to exhaustive single‑bridge fault injection. In every case, the proposed test set detected the fault, confirming 100 % fault coverage. Moreover, the algorithm that generates the test patterns runs in O(n + p) time, making it scalable to large designs that might be used in quantum‑dot or superconducting logic families.

Beyond the immediate result, the work has several broader implications:

• Design‑for‑Testability (DfT) – The derived test set can be incorporated early in the synthesis flow of reversible circuits, allowing designers to embed test points without incurring excessive overhead.

• Quantum‑Computing Relevance – Although the physical realization of a reversible gate in a quantum processor differs from CMOS, the logical structure of k‑CNOT gates is identical. Hence, the test methodology offers a blueprint for detecting wiring‑level defects in emerging quantum hardware, where bridging faults could arise from imperfect qubit coupling or control‑line crosstalk.

• Extension to Multiple Faults – The authors acknowledge that the single‑fault assumption is a simplification. Extending the analysis to multiple simultaneous bridges, stuck‑at faults, or delay faults constitutes a natural next step.

• Comparison with Existing Methods – Traditional reversible‑circuit testing techniques often rely on exhaustive truth‑table comparison or reversible‑logic‑specific fault models, leading to test sets that grow exponentially with circuit size. The linear‑scale result presented here represents a substantial improvement in test efficiency.

In conclusion, the paper demonstrates that AND‑EXOR based reversible circuits, despite being constructed from irreversible primitives, can be tested for single bridging faults with a remarkably small and predictable number of test vectors. The formula 3 n + ⌈log₂ p⌉ + 2 provides designers with a practical metric for estimating test effort, and the underlying methodology offers a solid foundation for future work on more complex fault models and on hardware implementations in quantum and nanotechnologies.