Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit’s primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

💡 Research Summary

The paper addresses the growing importance of reversible logic for low‑power CMOS, digital signal processing, cryptography, quantum computing, and optical information processing. Recognizing that existing reversible gates lack built‑in fault detection, the authors introduce a novel 4 × 4 parity‑preserving reversible gate named IG (Identity‑Gate). IG maps four input bits to four output bits while preserving the overall parity (the XOR of all inputs equals the XOR of all outputs). This property enables immediate detection of any single‑line fault, because a fault will flip the parity observable at the primary outputs.

Using IG as a primitive, the authors construct a fault‑tolerant reversible full adder (FTFA) with only two IG gates. Traditional reversible full adders typically require three or more gates, generate several garbage outputs, and need multiple constant inputs. In contrast, the FTFA uses two IGs, two constant inputs, and produces only two garbage outputs, dramatically reducing circuit depth and hardware overhead. The design computes the sum and carry‑out by first processing the three operand bits (A, B, Cin) through the first IG to generate intermediate parity signals, then feeding those signals into the second IG to obtain the final sum and carry. Because parity is preserved throughout, any single‑bit error in the adder is detectable at the outputs without additional error‑checking circuitry.

The FTFA serves as the fundamental building block for a reversible carry‑skip BCD (binary‑coded decimal) adder. BCD addition operates on 4‑bit groups representing decimal digits; rapid detection of a carry across groups is essential for performance. The authors embed an FTFA in each 4‑bit digit block and implement a reversible carry‑skip network that uses the parity signals from each block to decide whether the carry can be bypassed. This network is realized entirely with reversible gates, preserving the overall parity and fault‑detectability of the system.

Performance evaluation compares the proposed carry‑skip BCD adder with previously published reversible BCD adders. The new design achieves a gate count reduction of roughly 30 % (from 12–15 gates down to about 8), cuts the number of garbage outputs by more than half (from 6–8 to ≤ 4), and requires fewer constant inputs. Because reversible logic inherently minimizes energy dissipation, the reduced gate count and the carry‑skip mechanism together lower the average propagation delay by approximately 30 % and the dynamic power consumption accordingly.

Beyond the specific BCD adder, the paper discusses the broader applicability of IG and FTFA. Since IG is a 4‑bit parity‑preserving primitive, it can be composed to synthesize any arbitrary Boolean function in a reversible manner, making it suitable for constructing reversible multiplexers, subtractors, and more complex arithmetic‑logic units. In quantum computing contexts, the parity‑preserving property can be combined with quantum error‑correcting codes to provide an additional layer of fault detection without sacrificing reversibility.

In summary, the authors present a compact, parity‑preserving reversible gate (IG) that enables single‑fault detection, demonstrate its use in constructing a minimal‑overhead fault‑tolerant full adder, and leverage this adder to build an efficient reversible carry‑skip BCD adder. The proposed designs outperform existing reversible arithmetic circuits in terms of gate count, garbage outputs, constant inputs, delay, and power, offering a practical pathway for low‑power and quantum‑compatible digital systems.