Reversible circuits have applications in digital signal processing, computer graphics, quantum computation and cryptography. In this paper, a generalized k*k reversible gate family is proposed and a 3*3 gate of the family is discussed. Inverter, AND, OR, NAND, NOR, and EXOR gates can be realized by this gate. Implementation of a full-adder circuit using two such 3*3 gates is given. This full-adder circuit contains only two reversible gates and produces no extra garbage outputs. The proposed full-adder circuit is efficient in terms of gate count, garbage outputs and quantum cost. A 4-bit carry skip adder is designed using this full-adder circuit and a variable block carry skip adder is discussed. Necessary equations required to evaluate these adder are presented.
Deep Dive into Variable Block Carry Skip Logic using Reversible Gates.
Reversible circuits have applications in digital signal processing, computer graphics, quantum computation and cryptography. In this paper, a generalized kk reversible gate family is proposed and a 33 gate of the family is discussed. Inverter, AND, OR, NAND, NOR, and EXOR gates can be realized by this gate. Implementation of a full-adder circuit using two such 3*3 gates is given. This full-adder circuit contains only two reversible gates and produces no extra garbage outputs. The proposed full-adder circuit is efficient in terms of gate count, garbage outputs and quantum cost. A 4-bit carry skip adder is designed using this full-adder circuit and a variable block carry skip adder is discussed. Necessary equations required to evaluate these adder are presented.
The input vector of reversible circuit can be uniquely recovered from the output vector, that is, for each input pattern there is a unique output pattern. Logic computations that are not reversible necessarily generate heat irrespective of their implementation technologies. According to [2], zero energy dissipation would be possible only if the network consists of reversible gates. Synthesis of reversible logic circuits differs significantly from the synthesis of combinational (classical) logic circuits. Because in a reversible circuit the number of inputs must be equal to the number of outputs, every output can be used only once (i.e., no fan-out is permitted), and the resulting circuit must be acyclic.
Therefore, a good synthesis method must take into account the following rules:
- use as many outputs of every gate as possible, and thus minimize garbage (unused) outputs. 2. do not create more constant inputs (required to make an irreversible specification to a reversible one) to gates than is absolutely necessary.
more than one input, because each fan-out of two requires adding one copying circuit.
The rest of the paper is organized as follows: section 2 presents the families of reversible gates and their quantum cost. Section 3 presents a generalized k*k reversible gate and discusses an instance of this family of gates. Section 4 first establishes the minimum number of constant inputs and garbages are required to design a full adder circuit, and then composition of a new full adder circuit is proposed. Section 5 presents the design of a carry skip adder using the proposed full adder circuit for which it is used as basic building block. Section 6 presents a variable block carry skip adder block. Experimental results are shown in section 7. Section 8 concludes the paper. References are listed in section 9.
There exist many universal reversible gates [1,3,7,10,11]. The detailed cost of a reversible gate depends on any particular realization technology of quantum logic. According to [9], it is assumed that the cost of every 22 is the same. A 11 cost nothing, since it can be always included to arbitrary 22 gate that preceded or follows it. Thus, every permutation quantum gate will be build from 11 and 22 quantum primitives and its cost calculated as a total sum of 22 gates.
Using the well known realization of Toffoli gate with truly quantum 22 primitives, according to [9], the cost of Toffoli gate is five 22 gates, or simply, 5 as shown in figure 2. The cost of Fredkin gate is exactly the same as the cost of Toffoli gate [5], which is shown in figure 3. Peres gate can be realized with cost 4 [9]. This is the cheapest quantum realization of a complete (universal) permutation gate.
The full-adder output S (A⊕B⊕Cin), Cout ((A⊕B)Cin ⊕ AB) equations produce the same output (1,0) for the three distinct input combinations (0,0,1), (0,1,0), and (1,0,0). Therefore, to separate all repeated values of outputs S and Cout we need at least two garbage outputs. Thus, a total of outputs is 2+2 = 4. Since in reversible circuits number of inputs must be equal to number of outputs and there are three inputs (A, B, and Cin), at least one constant input is necessary.
A full adder implementation using two 33 Toffoli gates and two 22 Feynman gate is presented in [8].
The circuit requires four reversible gates, produces two garbage outputs and the quantum cost is of 10.
Another full adder implementation using four 3*3 Fredkin gates is presented in [6] The circuit requires four reversible gates, produces two garbage outputs and the quantum cost is of 20.
In this paper, we present a new full adder composition. It consists only of two Peres gate and the quantum cost is of 8, which is minimum than all of the existing compositions. This we will call Peres full-adder which shown in figure 6.
The carry skip adder reduces the delay due to the carry computation. Consider the full-adder’s operation. If either input is a logical 1, the cell will propagate the carry input to the carry output. Therefore, the i th fulladder carry input, Ci, will propagate the carry input to its carry output, Ci+1, when Pi = Ai⊕Bi. Multiple fulladders, called a block, can generate a “block” propagate signal to detour the incoming carry around to the block’s carry output signal. Figure 7 shows a 4-bit carry skip adder block. Each block is a small ripple carry adder producing the block’s sum and carry bits. The optimal number of blocks is found with Therefore, the optimal variable block size carry skip adder has delay
We compare our proposed full adder circuits with existing designs and result is shown in Table 1 and Table 2. In the previous paper Quantum costs of those circuits are not considered. We calculate the Quantum cost of those adder circuits and compare them with our proposed design. The analytical performance of the carry skip adder in [6] and our carry skip adder (Figure 7) is given in table 3. It is evident from Table 3 that our
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