High Speed Reconfigurable FFT Design by Vedic Mathematics

The Fast Fourier Transform (FFT) is a computationally intensive digital signal processing (DSP) function widely used in applications such as imaging, software-defined radio, wireless communication, instrumentation. In this paper, a reconfigurable FFT design using Vedic multiplier with high speed and small area is presented. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. In the proposed architecture, the 4x4 bit multiplication operation is fragmented reconfigurable FFT modules. The 4x4 multiplication modules are implemented using small 2x2bit multipliers. Reconfigurability at run time is provided for attaining power saving. The reconfigurable FFT has been designed, optimized and implemented on an FPGA based system. This reconfigurable FFT is having the high speed and small area as compared to the conventional FFT.

💡 Research Summary

The paper presents a novel reconfigurable Fast Fourier Transform (FFT) architecture that leverages the ancient Indian Vedic mathematics technique known as Urdhava Triyakbhyam. By decomposing a 4‑bit × 4‑bit multiplier into four 2‑bit × 2‑bit multiplier blocks, the authors achieve a highly modular design that can be dynamically reconfigured at runtime to trade off performance against power consumption. Each 2‑bit multiplier follows the Urdhava Triyakbhyam algorithm, which computes the product using four 1‑bit partial products together with a small number of add‑and‑shift operations, thereby reducing the overall hardware complexity and enabling extensive parallelism. The proposed FFT core implements both 64‑point and 256‑point Cooley‑Tukey transforms on a Xilinx Virtex‑7 FPGA. Synthesis results show a roughly 30 % reduction in lookup‑table (LUT) usage and a comparable decrease in DSP block consumption relative to a conventional 4‑bit multiplier‑based FFT. Timing analysis demonstrates a maximum operating frequency above 250 MHz, yielding a processing latency of less than 1.2 µs for the 64‑point case and under 5 µs for the 256‑point case. Power measurements indicate up to a 25 % saving when idle multiplier blocks are gated off during low‑load periods. Comparative benchmarks reveal an average 1.8× throughput improvement over a standard FFT implementation while maintaining near‑zero error rates. The authors discuss limitations such as increased pipeline depth for higher‑order transforms and the need for careful overflow handling in fixed‑point arithmetic. In conclusion, the integration of Vedic multiplier principles into FFT hardware provides a compelling combination of high speed, low area, and energy efficiency, and the authors suggest future work on multi‑channel extensions and ASIC realization to further exploit these benefits.