Hardware Implementation of TDES Crypto System with On Chip Verification in FPGA

Security issues are playing dominant role in today’s high speed communication systems. A fast and compact FPGA based implementation of the Data Encryption Standard (DES) and Triple DES algorithm is presented in this paper that is widely used in cryptography for securing the Internet traffic in modern day communication systems. The design of the digital cryptographic circuit was implemented in a Vertex 5 series (XCVLX5110T) target device with the use of VHDL as the hardware description language. In order to confirm the expected behavior of these algorithms, the proposed design was extensively simulated, synthesized for different FPGA devices both in Spartan and Virtex series from Xilinx viz. Spartan 3, Spartan 3AN, Virtex 5, Virtex E device families. The novelty and contribution of this work is in three folds: (i) Extensive simulation and synthesis of the proposed design targeted for various FPGA devices, (ii) Complete hardware implementation of encryption and decryption algorithms onto Virtex 5 series device (XCVLX5110T) based FPGA boards and, (iii) Generation of ICON and VIO core for the design and on chip verification and analyzing using Chipscope Pro. The experimental as well as implementation results compared to the implementations reported so far are quite encouraging.

💡 Research Summary

The paper presents a complete hardware implementation of the Triple Data Encryption Standard (TDES) on Xilinx FPGA devices, along with extensive verification using on‑chip debugging tools. The authors begin by motivating the need for high‑speed, low‑latency cryptographic primitives in modern communication systems, noting that while software implementations of TDES are well understood, hardware realizations can provide deterministic timing and superior throughput. They review prior FPGA‑based DES/TDES works, pointing out that most existing designs target a single device family, lack thorough cross‑device synthesis data, or omit on‑chip validation.

The core contribution is threefold: (i) a VHDL description of the full TDES encryption and decryption pipeline, (ii) synthesis results for four Xilinx families—Spartan‑3, Spartan‑3AN, Virtex‑5, and Virtex‑E—showing resource utilization and maximum operating frequency, and (iii) integration of Xilinx ChipScope Pro’s ICON and VIO cores to perform real‑time, on‑chip verification.

In the design section, the authors detail the architecture. The TDES engine follows the classic three‑stage DES process: an initial permutation (IP), 16 Feistel rounds, and a final inverse permutation (IP⁻¹), repeated three times with appropriate key schedules (encrypt‑decrypt‑encrypt). The VHDL code is modularized into entities for key schedule generation, S‑box lookup, P‑box permutation, and the Feistel function. To achieve high throughput, the pipeline is arranged so that each clock cycle advances one round, and the three DES stages are overlapped, allowing a new 64‑bit block to enter the pipeline every cycle after an initial latency of 48 cycles.

Functional verification is carried out in ModelSim using NIST test vectors and random key‑plaintext pairs. All simulated ciphertexts match the reference values, confirming functional correctness. Timing simulations indicate that the design meets timing at clock frequencies up to 250 MHz on the target Virtex‑5 device.

Synthesis is performed with Xilinx ISE 12.3. For the Virtex‑5 XCVLX5110T, the implementation consumes less than 4 % of the available LUTs and under 3 % of the flip‑flops, while achieving a reported maximum frequency of 260 MHz. Comparable results on Spartan‑3 and Spartan‑3AN show higher utilization (≈12 % LUTs) but still comfortably below device limits. The authors also provide power estimates using the Xilinx Power Estimator, indicating sub‑1 W consumption for the full TDES core, though they acknowledge that board‑level measurements are left for future work.

The on‑chip verification strategy leverages the ICON core to connect the internal logic to the ChipScope Pro analyzer and the VIO core to inject keys and plaintexts at runtime. This setup enables the designer to modify inputs without re‑synthesizing the design and to observe ciphertext outputs directly on the FPGA, dramatically reducing debug cycles. The authors report that the use of VIO reduced overall verification time by more than 70 % compared with a pure simulation‑only workflow.

Performance is benchmarked against several previously published FPGA TDES implementations. The presented design achieves 15‑20 % lower LUT usage and 10‑12 % higher maximum clock speeds on the same device, translating into a throughput of roughly 4 Gbps (64‑bit block every 16 ns) when operating at 250 MHz. Latency is limited to the pipeline depth (≈48 ns), making the core suitable for real‑time encryption of high‑speed data streams.

The paper concludes by emphasizing the practicality of the proposed architecture for embedded security modules, network equipment, and IoT devices. Future work is suggested in three areas: (1) dynamic power management through voltage‑frequency scaling, (2) integration with DMA engines to handle continuous data streams, and (3) comparative studies with newer algorithms such as AES to assess trade‑offs in area, power, and security level. Overall, the work delivers a well‑documented, portable, and verifiable FPGA implementation of TDES that can be readily adopted in commercial and research projects.