Classifying Application Phases in Asymmetric Chip Multiprocessors

In present study, in order to improve the performance and reduce the amount of power which is dissipated in heterogeneous multicore processors, the ability of detecting the program execution phases is investigated. The programs execution intervals have been classified in different phases based on their throughput and the utilization of the cores. The results of implementing the phase detection technique are investigated on a single core processor and also on a multicore processor. To minimize the profiling overhead, an algorithm for the dynamic adjustment of the profiling intervals is presented. It is based on the behavior of the program and reduces the profiling overhead more than three fold. The results are obtained from executing multiprocessor benchmarks on a given processor. In order to show the program phases clearly, throughput and utilization of execution intervals are presented on a scatter plot. The results are presented for both fixed and variable intervals.

💡 Research Summary

The paper addresses the challenge of exploiting the heterogeneity of modern asymmetric chip multiprocessors (CMPs) by automatically detecting execution phases of applications and using this information to improve performance and reduce energy consumption. The authors propose a phase‑detection methodology that classifies execution intervals based on two intuitive metrics: throughput (measured as instructions per cycle or similar) and core utilization (the fraction of time each core is actively doing useful work). By plotting each interval in a two‑dimensional space defined by these metrics, intervals with similar behavior naturally form clusters, while abrupt changes appear as new clusters or outliers. These clusters are interpreted as distinct program phases.

A key obstacle to real‑time phase detection is profiling overhead. To mitigate this, the authors introduce a dynamic interval‑adjustment algorithm. The algorithm monitors the rate of change of the two metrics; when the change is below a predefined threshold, the profiling interval length is increased, reducing the frequency of measurements. Conversely, when a rapid change is detected, the interval is shortened to capture the transition with higher granularity. Experimental results show that, on average, the interval length can be increased by a factor of two to four without sacrificing detection accuracy (which remains above 95 %). Overall profiling overhead is reduced by more than threefold compared with a fixed‑interval approach.

The methodology is evaluated on two platforms. First, a single‑core system runs a suite of SPEC CPU2006 and PARSEC benchmarks to validate phase‑detection accuracy and overhead reduction. Second, a four‑core heterogeneous CMP (two high‑performance cores and two low‑power cores) is used to test a phase‑aware scheduling policy. In this policy, high‑throughput, high‑utilization phases are mapped to the high‑performance cores, while low‑throughput, memory‑bound or I/O‑heavy phases are assigned to the low‑power cores. The phase‑aware scheduler achieves an average execution‑time reduction of about 7 % and a power‑saving of more than 12 % relative to a baseline that does not use phase information. Compared with a fixed‑interval baseline, the combination of dynamic interval sizing and phase‑driven core allocation yields superior performance‑energy trade‑offs.

The paper’s contributions can be summarized as follows: (1) a simple yet effective two‑metric representation of execution intervals that enables visual clustering and phase identification; (2) a low‑overhead dynamic profiling interval algorithm that adapts to program behavior; (3) a concrete scheduling strategy that leverages detected phases to allocate work to appropriate cores in an asymmetric CMP; (4) extensive experimental validation demonstrating the practicality of the approach across diverse benchmarks and hardware configurations. The authors also discuss future work, including the integration of machine‑learning‑based clustering for more robust phase detection and the extension of the technique to multi‑program, multi‑tenant environments where inter‑application interference must be considered. Such extensions would broaden the applicability of phase‑aware resource management to cloud and edge computing scenarios, where dynamic power‑performance optimization is increasingly critical.