Large Focal Plane Arrays for Future Missions

We outline the challenges associated with the development and construction of large focal plane arrays for use both on the ground and in space. Using lessons learned from existing JPL-led and ASU/JPL partnership efforts to develop technology for, and design such arrays and imagers for large focal planes, we enumerate here the remaining problems that need to be solved to make such a venture viable. Technologies we consider vital for further development include: (1) architectures, processes, circuits, and readout solutions for production and integration of four-side buttable, low-cost, high-fidelity, high-performance, and high-reliability CCD and CMOS imagers; (2) modular, four-side buttable packaging of CCD/CMOS imagers; (3) techniques and hardware to test and characterize the large number of chips required to produce the hundreds of flight-grade detectors needed for large focal-plane missions being conceived at this time; (4) ground based testbed needs, such as a large format camera mounted on a ground-based telescope, to field test the detectors and the focal plane technology solutions; and (5) validation of critical sub-components of the design on a balloon mission to ensure their flight-readiness. This paper outlines the steps required to provide a mature solution to the astronomical community with a minimal investment, building on years of planning and investments already completed at JPL.

💡 Research Summary

The paper presents a comprehensive roadmap for developing large focal‑plane arrays (FPAs) that will serve future ground‑based telescopes and space missions. Drawing on lessons learned from JPL‑led projects and the ASU/JPL partnership, the authors identify five critical technology areas that must be resolved to make large‑scale FPAs viable. First, they emphasize the need for four‑side buttable CCD and CMOS imagers that can be tiled without gaps, thereby maximizing fill factor and scientific throughput. Current commercial packaging is limited to two‑ or three‑side bonding, so new wafer‑level alignment, through‑silicon‑via (TSV) or micro‑bump interconnects, and thermal‑mechanical stress management solutions are required. Second, the paper advocates modular, four‑side buttable packaging that isolates each detector in a replaceable “cassette,” enabling rapid fault isolation and minimizing downtime in missions that demand hundreds to thousands of flight‑grade detectors. Third, the authors highlight the bottleneck of testing and characterizing the massive number of chips needed; they propose an automated test line with real‑time data processing, machine‑learning‑based defect classification, and integrated environmental stress screening (thermal, radiation, vibration) to reduce per‑chip test time to minutes and maintain a defect rate below 0.1 %. Fourth, a ground‑based testbed consisting of a large‑format camera mounted on an operational telescope is recommended to validate system‑level performance—image quality, noise, power, and thermal management—under real observing conditions. This step bridges the gap between laboratory prototypes and full‑scale scientific operations. Fifth, the authors suggest a high‑altitude balloon flight as a low‑cost, near‑space platform to demonstrate flight readiness of critical subsystems, including radiation tolerance, thermal control, and data‑link reliability, before committing to satellite deployment. Throughout the manuscript, the authors stress a staged approach: detector design and packaging, modular integration, high‑throughput testing, ground‑based validation, and balloon‑based flight verification. By leveraging existing JPL and ASU investments, the proposed strategy aims to deliver a mature, cost‑effective large‑FPA solution to the astronomical community with minimal additional funding, thereby accelerating the deployment of next‑generation wide‑field imagers for both terrestrial and space observatories.