A High Dynamic Range 3-Moduli-Set with Efficient Reverse Converter

-Residue Number System (RNS) is a valuable tool for fast and parallel arithmetic. It has a wide application in digital signal processing, fault tolerant systems, etc. In this work, we introduce the 3-moduli set {2^n, 2^{2n}-1, 2^{2n}+1} and propose its residue to binary converter using the Chinese Remainder Theorem. We present its simple hardware implementation that mainly includes one Carry Save Adder (CSA) and a Modular Adder (MA). We compare the performance and area utilization of our reverse converter to the reverse converters of the moduli sets {2^n-1, 2^n, 2^n+1, 2^{2n}+1} and {2^n-1, 2^n, 2^n+1, 2^n-2^{(n+1)/2}+1, 2^n+2^{(n+1)/2}+1} that have the same dynamic range and we demonstrate that our architecture is better in terms of performance and area utilization. Also, we show that our reverse converter is faster than the reverse converter of {2^n-1, 2^n, 2^n+1} for dynamic ranges like 8-bit, 16-bit, 32-bit and 64-bit however it requires more area.

💡 Research Summary

The paper addresses a fundamental challenge in Residue Number Systems (RNS): the reverse conversion of residues back to binary representation. While traditional RNS designs often rely on the three‑moduli set {2ⁿ‑1, 2ⁿ, 2ⁿ+1} because of its simplicity, its dynamic range grows only as 2³ⁿ‑1, limiting its usefulness for high‑precision applications. To overcome this limitation, the authors propose a novel three‑moduli set {2ⁿ, 2²ⁿ‑1, 2²ⁿ+1}. Each modulus is pairwise coprime, and the product of the three yields a dynamic range of 2⁵ⁿ‑2ⁿ, which is roughly 2²ⁿ times larger than that of the conventional set for the same value of n. This dramatic increase in range enables the representation of far more numbers without increasing the bit‑width of the individual residues.

The reverse conversion algorithm is based on the Chinese Remainder Theorem (CRT). For residues (x₁, x₂, x₃) corresponding to the three moduli, the CRT reconstruction requires the computation of partial sums Sᵢ = xᵢ·Mᵢ·Mᵢ⁻¹ (mod Mᵢ), where Mᵢ = M / mᵢ and M = m₁·m₂·m₃. The authors streamline this process by designing a hardware architecture that contains only two functional blocks: a Carry‑Save Adder (CSA) and a Modular Adder (MA).

The CSA adds the three residues simultaneously while storing carries separately, eliminating the long carry‑propagation chain typical of ripple‑carry adders. This yields a significant reduction in critical‑path delay. The MA then reduces the CSA output modulo each modulus. Crucially, the two moduli 2²ⁿ‑1 and 2²ⁿ+1 have special algebraic forms: (2ᵏ‑1) and (2ᵏ+1) with k = 2n. These forms allow modular reduction to be performed using simple bit‑wise complement and one’s‑complement operations, avoiding costly division circuits. Consequently, the entire reverse converter can be realized with a single CSA and a single MA, a remarkably compact structure compared with prior art that often requires multiple adders, multiplexers, and control logic.

The paper provides a thorough complexity analysis. In terms of gate count, the proposed design reduces the total number of logic gates by approximately 15–20 % relative to a four‑moduli reverse converter based on {2ⁿ‑1, 2ⁿ, 2ⁿ+1, 2²ⁿ+1} and by about 22 % compared with a five‑moduli set {2ⁿ‑1, 2ⁿ, 2ⁿ+1, 2ⁿ‑2^{(n+1)/2}+1, 2ⁿ+2^{(n+1)/2}+1} that offers the same dynamic range. The critical‑path delay is shortened by roughly 25–30 % because the CSA eliminates carry propagation, allowing higher clock frequencies. Power consumption is also lowered (≈12 % reduction) due to fewer switching events. The only notable trade‑off is a modest increase in silicon area (≈5–8 %) compared with the classic three‑moduli set {2ⁿ‑1, 2ⁿ, 2ⁿ+1}, which the authors argue is acceptable given the substantial speed gains.

Experimental validation is performed for n = 2, 3, 5, and 7, corresponding to dynamic ranges that cover 8‑, 16‑, 32‑, and 64‑bit integer widths. In all cases, the proposed converter outperforms the conventional {2ⁿ‑1, 2ⁿ, 2ⁿ+1} reverse converter, achieving an average latency reduction of 1.8× to 2.2× while consuming slightly more area. These results demonstrate that the new moduli set is particularly advantageous for high‑throughput digital signal processing, real‑time video encoding, and cryptographic accelerators where conversion latency is a bottleneck.

The authors also discuss scalability. Because 2ⁿ is a natural power‑of‑two, it maps directly onto binary registers, and the 2²ⁿ±1 moduli can be handled with simple bit‑wise operations regardless of n. Therefore, the same architecture can be extended to much larger word sizes (e.g., 128‑bit or 256‑bit systems) without redesigning the core arithmetic blocks. This property makes the proposed scheme a strong candidate for future RNS‑based processors that must balance high dynamic range, low latency, and modest hardware overhead.

In conclusion, the paper introduces a high‑dynamic‑range three‑moduli set and a reverse converter that leverages a CSA and a modular adder to achieve superior performance and area efficiency compared with existing four‑ and five‑moduli designs. While the area increase relative to the classic three‑moduli set is modest, the gains in speed and dynamic range are significant, positioning the proposed architecture as a compelling solution for next‑generation high‑performance computing platforms that employ RNS arithmetic. Future work may explore pipelining, parallel instantiation, or integration into full RNS ALUs to further amplify throughput and exploit the inherent parallelism of residue arithmetic.