Technologies for 3D Heterogeneous Integration

📝 Abstract

3D-Integration is a promising technology towards higher interconnect densities and shorter wiring lengths between multiple chip stacks, thus achieving a very high performance level combined with low power consumption. This technology also offers the possibility to build up systems with high complexity just by combining devices of different technologies. For ultra thin silicon is the base of this integration technology, the fundamental processing steps will be described, as well as appropriate handling concepts. Three main concepts for 3D integration have been developed at IZM. The approach with the greatest flexibility called Inter Chip Via - Solid Liquid Interdiffusion (ICV-SLID) is introduced. This is a chip-to-wafer stacking technology which combines the advantages of the Inter Chip Via (ICV) process and the solid-liquid-interdiffusion technique (SLID) of copper and tin. The fully modular ICV-SLID concept allows the formation of multiple device stacks. A test chip was designed and the total process sequence of the ICV-SLID technology for the realization of a three-layer chip-to-wafer stack was demonstrated. The proposed wafer-level 3D integration concept has the potential for low cost fabrication of multi-layer high-performance 3D-SoCs and is well suited as a replacement for embedded technologies based on monolithic integration. To address yield issues a wafer-level chip-scale handling is presented as well, to select known-good dies and work on them with wafer-level process sequences before joining them to integrated stacks.

💡 Analysis

3D-Integration is a promising technology towards higher interconnect densities and shorter wiring lengths between multiple chip stacks, thus achieving a very high performance level combined with low power consumption. This technology also offers the possibility to build up systems with high complexity just by combining devices of different technologies. For ultra thin silicon is the base of this integration technology, the fundamental processing steps will be described, as well as appropriate handling concepts. Three main concepts for 3D integration have been developed at IZM. The approach with the greatest flexibility called Inter Chip Via - Solid Liquid Interdiffusion (ICV-SLID) is introduced. This is a chip-to-wafer stacking technology which combines the advantages of the Inter Chip Via (ICV) process and the solid-liquid-interdiffusion technique (SLID) of copper and tin. The fully modular ICV-SLID concept allows the formation of multiple device stacks. A test chip was designed and the total process sequence of the ICV-SLID technology for the realization of a three-layer chip-to-wafer stack was demonstrated. The proposed wafer-level 3D integration concept has the potential for low cost fabrication of multi-layer high-performance 3D-SoCs and is well suited as a replacement for embedded technologies based on monolithic integration. To address yield issues a wafer-level chip-scale handling is presented as well, to select known-good dies and work on them with wafer-level process sequences before joining them to integrated stacks.

📄 Content

9-11 April 2008

©EDA Publishing/DTIP 2008

ISBN: 978-2-35500-006-5 Technologies for 3D Wafer Level Heterogeneous Integration

M.J. Wolf*, P. Ramm,** A. Klumpp**, H. Reichl* Fraunhofer IZM *Berlin/**Munich Contact: wolf@izm.fraunhofer.de

Abstract-3D integration is a fast growing field that encompasses different types of technologies. The paper addresses one of the most promising technology which uses Through Silicon Vias (TSV) for interconnecting stacked devices on wafer level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM has developed a post front-end 3D integration process which allows stacking of functional and tested FE-devices e.g. sensors, ASICs on wafer level as well as a technology portfolio for passive silicon interposer with redistribution layers and TSV.

I.
DRIVERS FOR 3D SYSTEM INTEGRATION Since several years packaging is driven by System in Package (SiP) solutions to meet the requirements of improved performance, miniaturization and cost reduction. This leads to a number of technologies where 3D system integration is one of the main potential drivers [1]. In general, the introduction of 3D integration technologies is driven by

• Form factor: Reduction of system volume, weight and footprint • Performance: Improvement of integration density and reduction of interconnect length leading to improved transmission speed and reduced power consumption • High volume low cost production: Reduction of processing costs for, e.g., mixed technologies • New applications: e.g. ultra compact camera and detector systems and small wireless sensor nodes

In competition to Systems on Chip (SoC) solutions, the 3D wafer level system integration enables the combination of different optimized production technologies. In addition, 3D integration is a possible solution to overcome the “wiring crisis” caused by signal propagation delay, both, at board and at chip level, because it allows minimal interconnection lengths and the elimination of speed-limiting intra- and inter- chip interconnects. The introduction of very advanced microelectronic systems, as e.g. 3D image processors, will be mainly driven by the enhancement of performance. The potential for low cost fabrication will be a further key aspect for future applications of 3D integration as well. Today, the fabrication of Systems on Chip (SoC) is based on embedding multiple technologies by monolithic integration. But there are serious disadvantages: The chip partition with the highest complexity drives the process technology which leads to a “cost explosion” of the overall system. In contrast to this, suitable 3D integration technologies enable the combination of different optimized base technologies, e.g. MEMS, CMOS, etc., with the potential of low cost fabrication through high yield and high miniaturization degree. II.
ADVANCED 3D WAFER LEVEL SYSTEM INTEGRATION TECHNOLOGIES 2.1 THROUGH SILICON VIA (TSV) TECHNOLOGY

Wafer level packaging technologies, e.g. CSP with redistribution layers or flip chip mounted devices on wafer, are already introduced in high volume production. Currently, different technologies which use Through Silicon Vias (TSV) in active or passive silicon devices are in development to satisfy the need to increase performance and functionality while reducing size, power and cost of the system. Today, there are two mainstreams to realize TSVs. One is the implementation into the front-end CMOS process and the second is a post front end process (via first/via last) process. Both scenarios have pros and cons and the selection depends on application and infrastructure. The post front end process allows the realization of compact 3D system architectures as a packaging task with complete tested device wafers independent from the device wafer manufacturer. Key process technologies enabling 3D architectures with TSV interconnects include:

• via formation with high aspect ratio, • isolation, barrier and seed deposition, • via metal filling, redistribution lines (RDL),
• wafer thinning, • thin wafer handling and transfer processes, • assembly: wafer/chip alignment, adjusted bonding

Most of those 3D technologies are quite new to the packaging 9-11 April 2008

©EDA Publishing/DTIP 2008

ISBN: 978-2-35500-006-5 industry and require a FE/BE infrastructure. That’s why 3D-IC architectures are today still at the R&D stage, even in the largest IC companies, but they are in focus as a potential solution with a high priority. Many of the key technical issues and challenges for TSV interconnects are not fully resolved yet. There are also a number of alternative technologies, e.g.: • process integration: via-first vs. via-last
• via filling: materials (e.g. poly Si, Cu, W, conductive polymer, metal paste) and techniques (e.g. electro- plating, CVD

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