A Logic Programming Framework for Combinational Circuit Synthesis

Logic Programming languages and combinational circuit synthesis tools share a common “combinatorial search over logic formulae” background. This paper attempts to reconnect the two fields with a fresh look at Prolog encodings for the combinatorial objects involved in circuit synthesis. While benefiting from Prolog’s fast unification algorithm and built-in backtracking mechanism, efficiency of our search algorithm is ensured by using parallel bitstring operations together with logic variable equality propagation, as a mapping mechanism from primary inputs to the leaves of candidate Leaf-DAGs implementing a combinational circuit specification. After an exhaustive expressiveness comparison of various minimal libraries, a surprising first-runner, Strict Boolean Inequality “<” together with constant function “1” also turns out to have small transistor-count implementations, competitive to NAND-only or NOR-only libraries. As a practical outcome, a more realistic circuit synthesizer is implemented that combines rewriting-based simplification of (<,1) circuits with exhaustive Leaf-DAG circuit search. Keywords: logic programming and circuit design, combinatorial object generation, exact combinational circuit synthesis, universal boolean logic libraries, symbolic rewriting, minimal transistor-count circuit synthesis

💡 Research Summary

The paper presents a novel framework that bridges logic programming—specifically Prolog—and exact combinational circuit synthesis. The authors observe that both domains share a fundamental combinatorial search over logical formulae, and they exploit Prolog’s built‑in backtracking, unification, and term‑grammar mechanisms to generate candidate circuit structures efficiently.

The core data structure is a Leaf‑DAG (directed acyclic graph whose only nodes with outgoing edges are internal operators, while leaves may have multiple incoming edges). This mirrors Prolog terms that can contain repeated variables, enabling a natural encoding of circuits where shared sub‑expressions become merged leaves. The synthesis algorithm proceeds in three phases:

1. Pre‑processing / Rewriting: A library‑specific rewriting module simplifies the target Boolean specification (given in symbolic, CNF, or DNF form) and produces an upper bound on the number of gates. This bound is used both as a timeout guard and as a heuristic solution if exact synthesis fails.

2. Enumerative Search in Cost‑Increasing Order: Candidate trees are generated incrementally by size. The tree generator respects Catalan number limits for binary trees, while a separate “functions_from/2” predicate enumerates all possible bindings of primary inputs to leaf occurrences. Crucially, this enumeration is performed without constructing concrete term structures; only logical variable bindings are trailed, which makes the backtracking overhead negligible. For a circuit with N inputs and M internal nodes, the total number of leaf‑DAGs explored is Catalan(M) × N^(M+1).

3. Fast Boolean Evaluation via Bit‑String Truth Tables: Each variable is mapped to a fixed bit‑string integer representing its truth table (e.g., for n inputs the integer has 2^n bits). Prolog’s bitwise integer operators (&, |, #, etc.) are then used to compute the truth table of a composite node instantly. This allows the algorithm to test candidate Leaf‑DAGs against the specification by a single integer equality test, avoiding any recursive evaluation or additional backtracking.

The authors then conduct an extensive expressiveness comparison of several universal Boolean libraries. They count how many gates are required to realize all sixteen 2‑argument Boolean operators using each library. NAND or NOR alone need 46 gates, whereas the pair ( < , 1 )—strict Boolean inequality together with the constant 1—requires only 28 gates. Adding equality or other operators can reduce the count further (e.g., ( < , = , 1 ) needs 21). This demonstrates that non‑traditional libraries can be dramatically more compact than the classic NAND/NOR bases.

Section 5 focuses on the ( < , 1 ) library. The strict inequality A < B is equivalent to ¬A ∧ B, providing a form of inverted conjunction. Moreover, XOR can be expressed as (A < B) ⊕ (B < A), showing that the library can capture notoriously hard‑to‑synthesize functions. The authors devise a rewriting system specific to ( < , 1 ) that simplifies expressions before the exhaustive search, dramatically pruning the search space.

Section 6 presents a CMOS transistor implementation of the <‑gate. The gate can be built with two PMOS and two NMOS transistors, comparable to NAND but often with fewer interconnects, while the constant 1 requires no active circuitry. Consequently, circuits built from ( < , 1 ) achieve lower transistor counts, area, and power than equivalent NAND/NOR implementations.

The paper also discusses integration with constraint handling rules (CHR) for future extensions such as layout, routing, and technology mapping, suggesting that a full design flow could be expressed within the same logic‑programming environment.

In summary, the contribution is threefold:

• A clean Prolog‑based exact synthesis engine that leverages logical variable bindings and bit‑string truth tables for ultra‑fast equivalence checking.
• An empirical study showing that the strict Boolean inequality together with constant 1 forms a highly expressive, low‑cost universal library, outperforming traditional NAND/NOR bases in gate and transistor count.
• A practical implementation that combines symbolic rewriting with exhaustive Leaf‑DAG enumeration, offering a realistic tool for exact combinational synthesis while remaining compact and extensible.

Overall, the work revives interest in logic programming for hardware design, demonstrates that non‑standard Boolean bases can yield superior hardware metrics, and provides a solid foundation for future research on Prolog‑centric CAD tools.