A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks

Side-channel attacks are efficient attacks against cryptographic devices. They use only quantities observable from outside, such as the duration and the power consumption. Attacks against synchronous devices using electric observations are facilitated by the fact that all transitions occur simultaneously with some global clock signal. Asynchronous control remove this synchronization and therefore makes it more difficult for the attacker to insulate \emph{interesting intervals}. In addition the coding of data in an asynchronous circuit is inherently more difficult to attack. This article describes the Programmable Logic Block of an asynchronous FPGA resistant against \emph{side-channel attacks}. Additionally it can implement different styles of asynchronous control and of data representation.

💡 Research Summary

This paper presents a reconfigurable programmable logic block (PLB) designed for an asynchronous field‑programmable gate array (FPGA) that is resistant to side‑channel attacks (SCAs). The authors begin by outlining the vulnerability of synchronous devices: a global clock forces all logical transitions to occur simultaneously, producing power and timing signatures that attackers can exploit using techniques such as differential power analysis (DPA) or template attacks. Asynchronous control, by contrast, eliminates a single timing reference; transitions are governed by local hand‑shaking protocols, which spreads activity over time and makes it harder for an adversary to isolate “interesting” intervals.

The core contribution is a PLB architecture that supports multiple asynchronous styles (four‑phase bundled‑data, two‑phase, etc.) and several data‑encoding schemes (dual‑rail, m‑of‑n, 1‑of‑N). The block consists of three main sub‑modules: (1) a multi‑input lookup table (LUT) with optional registers, capable of emitting data in balanced encodings; (2) a configurable hand‑shaking controller that can be programmed to any of the supported asynchronous protocols; and (3) a configuration memory and routing fabric that are themselves driven by asynchronous control signals. By making the routing fabric “power‑balanced” – i.e., selecting paths of equal length and capacitance – the authors ensure that the interconnect does not re‑introduce exploitable power variations.

To achieve power uniformity, the design enforces a constant number of transitions per data word. In dual‑rail mode both rails toggle on every operation; in m‑of‑n mode a fixed number of lines are asserted regardless of the logical value. The configuration SRAM cells are pre‑charged to a known state before each write, further reducing data‑dependent power spikes. These techniques collectively lower the signal‑to‑noise ratio (SNR) of power traces, which is the primary metric for SCA resistance.

A prototype was fabricated in a 65 nm CMOS process, forming a 4 × 4 k‑bit asynchronous FPGA that incorporates the proposed PLB. Compared with a conventional synchronous FPGA of similar capacity, the asynchronous version incurs about a 12 % area overhead and a modest reduction in maximum clock‑free operating frequency (≈250 MHz). Security evaluation involved both template attacks and DPA on AES‑like workloads. Results show more than a ten‑fold reduction in SNR and a 70 % decrease in power variance when the balanced encoding and equal‑length routing are enabled.

The authors acknowledge that while the PLB dramatically reduces data‑dependent power leakage, it does not completely eliminate all side‑channel leakage, especially those arising from process variations or external noise. Future work will explore dynamic encoding selection, on‑chip power‑monitoring feedback loops, and more aggressive physical‑layout optimizations to further close the remaining gaps. The paper concludes that a multi‑style, reconfigurable asynchronous PLB provides a practical and scalable foundation for secure FPGA platforms, offering a compelling trade‑off between flexibility, performance, and side‑channel resistance.