Energy and Time Efficient Scheduling of Tasks with Dependencies on Asymmetric Multiprocessors

In this work we study the problem of scheduling tasks with dependencies in multiprocessor architectures where processors have different speeds. We present the preemptive algorithm “Save-Energy” that given a schedule of tasks it post processes it to improve the energy efficiency without any deterioration of the makespan. In terms of time efficiency, we show that preemptive scheduling in an asymmetric system can achieve the same or better optimal makespan than in a symmetric system. Motivited by real multiprocessor systems, we investigate architectures that exhibit limited asymmetry: there are two essentially different speeds. Interestingly, this special case has not been studied in the field of parallel computing and scheduling theory; only the general case was studied where processors have $K$ essentially different speeds. We present the non-preemptive algorithm ``Remnants’’ that achieves almost optimal makespan. We provide a refined analysis of a recent scheduling method. Based on this analysis, we specialize the scheduling policy and provide an algorithm of $(3 + o(1))$ expected approximation factor. Note that this improves the previous best factor (6 for two speeds). We believe that our work will convince researchers to revisit this well studied scheduling problem for these simple, yet realistic, asymmetric multiprocessor architectures.

💡 Research Summary

The paper investigates the scheduling of precedence‑constrained tasks on asymmetric multiprocessor platforms, where processors have heterogeneous speeds. The authors focus on two complementary objectives: minimizing energy consumption without increasing the makespan, and achieving makespan that is at least as good as (often better than) that obtained on a symmetric platform with the same average speed and number of processors.

Model and assumptions

• The platform consists of m processors. A subset mₛ are “fast” with speed s > 1; the remaining m – mₛ are “slow” with unit speed.
• Each task has unit processing time; the precedence graph is a DAG (or a collection of chains after a maximal chain decomposition).
• Power consumption of processor k is proportional to c(k)^α·t where c(k) is its speed and α > 1 is a constant (convex power model).
• Processor‑reassignment overhead is assumed negligible, and preemption is allowed unless explicitly forbidden.

1. Energy‑saving post‑processing: “Save‑Energy”
Given any feasible schedule, the algorithm splits the timeline into intervals where no preemptions or completions occur. Within each interval it attempts to “fill holes” by moving work from faster to slower processors. The key optimality condition (Theorem 1) states that a schedule is energy‑optimal iff no such move can reduce total energy while keeping the makespan unchanged. Theorem 2 further shows that, when a move is possible, the most energy‑saving target speed is the one closest to α⁻¹·c(u) (for α = 2 this is simply c(u)/2). The algorithm proceeds greedily, always assigning a task fragment to the lowest speed that can accommodate it without delaying any other task. Complexity is O(m²·τ₀²) where τ₀ is the number of intervals; in practice τ₀ is small because preemptions are limited. The authors prove that the algorithm never increases makespan and can even shorten it when the original schedule contains idle time on fast processors.

2. Time‑efficiency of asymmetric platforms
Theorem 3 establishes that for any list of r chains, a preemptive schedule on an asymmetric platform (with the same average speed s′ and total processor count m) achieves a makespan no larger than the optimal symmetric schedule. The proof constructs a schedule for the asymmetric machine by mapping each time slice of the optimal symmetric schedule onto the asymmetric processors in order, thereby preserving the average processing speed. If the symmetric schedule ever leaves a processor idle, the asymmetric schedule can use the faster processors more intensively, yielding a strictly smaller makespan. Theorem 4 extends this result to arbitrary DAGs, confirming that asymmetry never harms optimal makespan under the given assumptions.

3. Near‑optimal makespan for two‑speed systems: “Remnants”
Most prior work considered K distinct speeds; the special case K = 2 (fast and slow) had not been studied in depth. The authors present a non‑preemptive algorithm called “Remnants”. After sorting chains by length, the algorithm first packs as many whole chains as possible onto the fast processors. The remaining “remnant” tasks are distributed among the slow processors using a probabilistic selection that balances load. A refined analysis of a recent scheduling method shows that the expected makespan of “Remnants” is at most (3 + o(1)) times optimal, improving the previous best factor of 6 for two‑speed systems. The analysis leverages the fact that only two speed levels exist, allowing tighter bounds on the contribution of slow processors to the overall schedule length.

4. Contributions and implications

• Introduces a practical post‑processing step that can be applied to any existing schedule to reduce energy without sacrificing performance.
• Provides rigorous proofs that asymmetry is never detrimental to makespan, encouraging hardware designers to adopt heterogeneous cores for energy‑performance trade‑offs.
• Delivers the first dedicated algorithmic treatment of the two‑speed case, achieving a substantially better approximation ratio than the generic K‑speed results.

5. Limitations and future directions
The work assumes unit‑size tasks, negligible preemption overhead, and a simple convex power model. Real workloads exhibit variable execution times, memory‑bandwidth constraints, and non‑convex power characteristics (e.g., DVFS curves). Moreover, the “Save‑Energy” algorithm requires knowledge of the entire schedule upfront, which may not be feasible in online or dynamic environments. Extending the techniques to online settings, incorporating heterogeneous task sizes, and accounting for communication costs are natural next steps.

In summary, the paper bridges the gap between energy‑aware and time‑aware scheduling on heterogeneous multiprocessors, offering both theoretical guarantees and algorithmic tools that are directly applicable to modern chip‑multiprocessor designs featuring a few high‑performance cores alongside many energy‑efficient cores.