A topological formal treatment for scenario-based software specification of concurrent real-time systems

Real-time systems are computing systems in which the meeting of their requirements is vital for their correctness. Consequently, if the real-time requirements of these systems are poorly understood and verified, the results can be disastrous and lead to irremediable project failures at the early phases of development. The present work addresses the problem of detecting deadlock situations early in the requirements specification phase of a concurrent real time system, proposing a simple proof-of-concepts prototype that joins scenario-based requirements specifications and techniques based on topology. The efforts are concentrated in the integration of the formal representation of Message Sequence Chart scenarios into the deadlock detection algorithm of Fajstrup et al., based on geometric and algebraic topology.

💡 Research Summary

The paper addresses the early‑stage detection of deadlocks in concurrent real‑time systems by integrating scenario‑based requirements specifications, expressed as Message Sequence Charts (MSCs), with topological deadlock detection techniques. The authors first formalize MSCs using process algebra (ACP) as defined in the ITU Z‑120 standard, representing each interaction as either an “out” (process → resource) or “in” (resource → process) operation with lock/unlock semantics. Parallel composition and a state operator are employed to capture the interleaving of independent processes and to enforce the basic static requirement that a message must be sent before it is received.

Next, the concurrent system is mapped onto an n‑dimensional unit cube (Iⁿ), where each axis corresponds to a distinct process. The execution of a process is represented by a monotonic trajectory from 0 to 1 along its axis, with lock (P) and unlock (V) actions placed at specific points. The combined trajectories of all processes form a “progress graph,” a geometric representation of the system’s state space. Within this space, three regions are identified: safe (allowable executions), forbidden (mutual‑exclusion holes that cannot be traversed), and unsafe (holes that correspond to deadlock states).

The core verification engine is the deadlock detection algorithm introduced by Fajstrup et al. (2015). This algorithm exploits homotopy theory: two execution paths that can be continuously deformed into each other are considered equivalent, while paths separated by forbidden regions are not. By checking whether any admissible path from the initial state (0,…,0) to the final state (1,…,1) must cross an unsafe region, the algorithm determines the presence of a deadlock without exhaustive state‑space exploration.

The authors implement a proof‑of‑concept prototype that automates the following workflow: (1) parse MSC diagrams, (2) extract processes, resources, and lock/unlock messages, (3) generate the corresponding process‑algebra expressions, (4) map each process to a coordinate axis in the unit cube, (5) construct the progress graph, and (6) apply the topological algorithm to detect forbidden/unsafe regions. Figure 7 in the paper illustrates a simple example where one MSC scenario yields a safe execution path, while another leads to a deadlock, both visualized as distinct trajectories in the cube.

The contribution lies in bridging a widely used, visual requirements language (MSC) with rigorous topological methods, thereby offering a mathematically sound yet practically accessible means of early deadlock detection. The approach reduces the combinatorial explosion typical of traditional model‑checking by focusing on geometric properties rather than enumerating all interleavings.

However, the study has limitations. It assumes that all communications are lock/unlock messages, ignoring richer protocol features, timing constraints, or asynchronous failures such as message loss. The prototype remains at a conceptual level; scalability to large industrial systems, performance benchmarks, and automated tool integration are not addressed. Moreover, the continuous‑space abstraction may overlook discrete error behaviours that are critical in real‑time environments.

In conclusion, the paper demonstrates a novel integration of MSC‑based scenario modeling with algebraic topology for deadlock analysis, providing a promising direction for early‑phase verification of concurrent real‑time software. Future work is suggested to extend the MSC language coverage, incorporate timing analysis, evaluate scalability, and develop a full‑featured verification toolchain suitable for industrial adoption.