An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories

Shrinking transistor size makes the reliability issue become a major challenge of system-on-chip (SOC) designs. Nowadays SOCs usually consists of many memory cores, which are usually the densest portion with the smallest feature size. Thus the reliability of memory cores has heavy impact on the reliability of SOCs. Reliability enhancement techniques for memory cores during life time thus is imperative. Conventional memory BIST (off-line BIST) is a promising approach for embedded memory testing and diagnosis [1,7,10,16], which is helpful for improving the yield of memories during manufacturing phase. However, off-line BISTs cannot be used for testing memories during life time. Thus efficient reliability enhancement techniques for memories should be developed. Online and transparent (periodic) testing are two widely used methodologies for ensuring correct operation of memories during life time. Concept of transparent testing, which leaves the original contents of the circuit under test unchanged after the testing is completed, has been used for the application of memory testing [3,6,8,9,[11][12][13][17][18][19]. One major advantage of transparent testing is that it can ensure the reliability of storage data during a life-time operation. On the other hand, transparent testing provides better fault coverage than nontransparent testing for unmodeled faults. Thus, unmodeled faults not detected by the manufacturing testing will be discovered at an early stage of the product life [12].

Several transparent test schemes have been reported in [3,6,8,9,[11][12][13][17][18][19]. These schemes transform the march tests, which have been widely used to test random access memories, into transparent march tests. In [11,12], a systematic approach for transforming a march test into a transparent march test is presented. The transformation rules consist of two phases-generation of transparent march test and generation of signature prediction test. In [3,8,17], the method from [11] is applied to the tests for detecting pattern-sensitive faults and single V-coupling faults described in [2]. Later a symmetric transparent test methodology is proposed in [18]. In this methodology, if the transformed transparent test is not symmetric, then an additional state is added to make it be symmetric. This causes that the final content of the signature analyzer (e.g., MISR) is zero if no faults exist in the memory under test. Thus this methodology can reduce the test time by removing the signature prediction test. Automatic generation of symmetric transparent march tests is also proposed in [19]. However, the transparent tests described above all have the problem of aliasing.

Recently, transparent test schemes without the aliasing problem have been reported in [9,13]. In [9], a transparent test approach using dynamic power supply current (DPSC) is presented. Instead of generating a signature, the DPSC transparent testing detects the RAM faults by using a current sensor. A transparent online memory test (TOMT) reported in [13] has been developed for online testing of word-oriented memories with parity or Hamming protection. TOMT introduces the concept of concurrent error detection and correction to eliminate the requirement of signature generation and to avoid the interference of normal system operation. So far, however, all the transparent tests for word-oriented memory are not time efficiency. For example, the transparent test scheme reported in [11,12] performs the bit-oriented operations to all the bits of each word. Another example, TOMT also executes bit-wise ma-nipulations in word-oriented memory testing. Therefore, short transparent tests for word-oriented memories need to be developed. Moreover, shorter test time can reduce the probability of interference of normal system operation, since transparent tests usually are executed in idle state of systems.

This paper presents an efficient transparent test scheme for word-oriented memories. A systematic algorithm is used for transforming a bit-oriented march test into a transparent word-oriented march test. Consider an AE¢ -bit memory and a bit-oriented march test with È Read/Write operations in which there are Q Read operations. Time complexity of the transparent word-oriented march test converted by the proposed algorithm is (È •5log ¾ )AE . Also, time complexity of the corresponding signature prediction test is (É•2log ¾ )AE . The transformed transparent march test has shorter test time compared with that proposed in previous works. For example, if a memory with 32-bit words is tested with March C , the time complexity of the transparent test transformed by the proposed scheme is only about 56% or 19% time complexity of the transparent test converted by the scheme reported in [12] or [13].

The rest of this paper is organized as follows. Section 2 reviews typical functional RAM faults and defines the notation for representing algorithms. Section 3 describes the transformation rules f

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