A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver

CHAVET Cyrille1, COUSSY Philippe2, URARD Pascal1, MARTIN Eric2 1STMicroelectronics, Crolles, FRANCE. {firstname.lastname@st.com} 2LESTER Lab, UBS University, CNRS FRE 2734. {firstname.lastname@univ-ubs.fr}

Abstract— This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space- Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism…), and formalizes communication constraints through a Resource Constraints Graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.

I. INTRODUCTION

The ever growing complexity of applications and the shrinking time-to-market lead the designers to reuse heterogeneous IP cores in Systems-On-a-Chip (SoC) which integration generates communication problems. System integrators can use standard interfaces such as Virtual Component Interface proposed by VSIA [12] and Open Core Protocol proposed by the OCP International Partnership [13]. However, in addition to the protocol aspects, SoC designers also have to synchronize components and to buffer data in order to ensure system behavior and to meet timing constraints. In [10] authors propose to automatically generate simulation wrappers for MPSoC architectures. Based on communication templates, [7] presents a generic interface unit architecture for communication synthesis in a platform-based design approach. In [1] a multiplexer/demultiplexer and FIFO-based interface architecture is used. In [6], the authors propose a systematic way of interfacing data- flow hardware accelerators (IP core) for their integration in a system on chip. Their interface architecture is based on FIFO (queue) storage elements and a Direct Memory Access module (DMA). They assume that the IP are data synchronized (i.e. at each clock cycle a data is presented and read). However, these previous approaches assumed that the sequence of produced data is the same as the sequence of consumed data (no re-ordering). Moreover, FIFO sizes are computed by a “set and simulate” approach.
Concerning Digital Signal Processing (DSP) applications, an MPSoC architecture may not be an adapted solution, and optimized hardware accelerator –composed of a set of computing blocks communicating through point-to-point links- are still needed in the SoC context. Obviously, interfacing DSP’s blocks greatly impacts the quality of the system (throughput, area, power consumption…), that’s why efficient communication adapter design is still one of the most important points in complex system design. In fact, using Input/Output (I/O) wrappers can introduce unnecessary memorizing elements. Such wrappers may be needed in order to solve data reordering problems that can arise from the IP core integration. In [8] the authors aim at determining at compile time whether a FIFO is sufficient for every producer/consumer pair of a Kahn Process Network. When the sequence of produced data is different from the sequence of consumed data, extra storage and control on the consumer side is proposed [11]. This extra module includes a CAM (Content Addressable Memory) where data are addressed using a hash table. This solution enables the implementation of non- deterministic communications, but it does not allow minimizing of the adapter overhead since overlapping of input and output data is not possible. In [2], a formal technique for hardware interface design is proposed. A generic interface model targeted by the communication synthesis is used. The low-level timing constraints can include strict timing specifications or data transfer schedule. The interface synthesis is carried out by an allocation procedure of data storage components (FIFO, LIFO and register). However, the size of storage elements is not computed or even taken into account during the design process. The proposed methodology is based on NP-complete maximum clique algorithm. In [9] the authors develop a system-level IP reuse methodology where designs are described in three layers. Data transfer and data storage optimizations are done by reorganizing loop indexing and loop nesting. Unfortunately, the authors do not present the technique they use to p

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