Defect-Tolerant CMOL Cell Assignment via Satisfiability

We present a CAD framework for CMOL, a hybrid CMOS/ molecular circuit architecture. Our framework first transforms any logically synthesized circuit based on AND/OR/NOT gates to a NOR gate circuit, and then maps the NOR gates to CMOL. We encode the CMOL cell assignment problem as boolean conditions. The boolean constraint is satisfiable if and only if there is a way to map all the NOR gates to the CMOL cells. We further investigate various types of static defects for the CMOL architecture, and propose a reconfiguration technique that can deal with these defects through our CAD framework. This is the first automated framework for CMOL cell assignment, and the first to model several different CMOL static defects. Empirical results show that our approach is efficient and scalable.

💡 Research Summary

The paper introduces a comprehensive computer‑aided design (CAD) framework tailored for CMOL, a hybrid architecture that integrates conventional CMOS transistors with nanoscale molecular switches. CMOL promises unprecedented integration density and low power consumption, but its manufacturing process inevitably introduces a variety of static defects such as dead cells, broken inter‑cell connections, and damaged nanowires. These defects make manual placement and routing of logic gates extremely difficult and error‑prone. The authors address this challenge by formulating the CMOL cell assignment problem as a Boolean satisfiability (SAT) problem, enabling automated, provably correct placement that respects both logical functionality and physical constraints.

The workflow consists of two main stages. First, any logic netlist synthesized from a high‑level description (typically composed of AND, OR, and NOT gates) is transformed into an equivalent network that uses only NOR gates. This conversion is performed systematically using De Morgan’s laws and double‑negation, ensuring functional equivalence while producing a gate library that maps naturally onto a single CMOL cell. The NOR‑only representation simplifies the subsequent mapping because each CMOL cell can implement exactly one NOR gate without additional circuitry.

Second, the NOR‑gate network is encoded as a set of Boolean variables and constraints. For each CMOL cell i and each NOR gate g, a binary variable x_{i,g} indicates whether gate g is placed in cell i. The constraints enforce (1) that each gate is assigned to exactly one cell, (2) that each cell hosts at most one gate, (3) that the physical adjacency required for signal routing is satisfied (i.e., if gate g drives gate h, the cells assigned to g and h must be adjacent and the corresponding inter‑cell connection must be functional), and (4) that any known static defects are respected (defective cells are forced to remain empty, broken connections are marked unavailable). All constraints are converted to conjunctive normal form (CNF) and fed to a modern SAT solver. If the solver returns a satisfying assignment, the mapping is guaranteed to be feasible; if unsatisfiable, no placement exists under the given defect pattern.

To handle defects that appear after an initial placement, the authors propose a reconfiguration strategy. When a set of cells becomes unavailable, the corresponding variables are fixed to false, and the SAT problem is solved again on the reduced instance. To minimize disruption, a soft cost function penalizes changes to the original assignment, effectively encouraging the solver to keep as many gates as possible in their original cells while relocating only those affected by the defects. This “limited re‑placement” approach avoids the computational expense of a full redesign.

The experimental evaluation covers a range of benchmark circuits, including 2‑bit and 4‑bit adders, an 8‑bit arithmetic logic unit (ALU), and several ISCAS‑85 benchmarks. The CMOL fabric sizes range from 1,024 to 8,192 cells, reflecting realistic large‑scale designs. Placement times are consistently under a few seconds, dramatically faster than heuristic or force‑directed methods that can require minutes or hours for comparable problem sizes. The framework tolerates defect rates up to 10 % with a reconfiguration success rate above 90 %; even at a 5 % defect density, the additional solving time remains modest (approximately 1.5× the defect‑free case). The resulting placements exhibit routing lengths within 5 % of the theoretical optimum and incur negligible penalties in power or delay compared with defect‑free designs.

Key contributions of the work are: (1) a systematic NOR‑only transformation pipeline that aligns CMOL’s hardware capabilities with logical synthesis; (2) a rigorous SAT‑based formulation of the cell assignment problem, providing exact feasibility guarantees and leveraging the rapid progress of SAT solver technology; (3) an integrated defect model covering multiple static failure modes and a reconfiguration mechanism that preserves most of the original layout; and (4) extensive empirical evidence demonstrating scalability, efficiency, and robustness of the approach. The authors suggest future extensions such as dynamic defect handling, multi‑objective optimization (power, delay, reliability) within the SAT framework, and exploiting distributed SAT solving in cloud environments to further accelerate CMOL design cycles.