Implementation of True Random Number Generator based on Double-Scroll Attractor circuit with GST memristor emulator

1 Implementation of T rue Random Number Generator based on Double-Scroll Attractor circuit with GST memristor emulator T ogzhan Abzhanov a, Irina Dolzhikov a, Student Member , IEEE, Alex Pappachen James, Senior Member , IEEE, Electrical and Computer Engineering Department, Nazarbayev Uni versity , Astana, Kazakhstan Abstract —The cryptographic security pro vided by various techniques of random number generator (RNG) construction is one of the developing r esearches ar eas today . Among various types of RNG, the true random bit generator (TRBG) can be considered as the most unpredictable and most secured because its randomness seed is generated from chaotic sour ces. This paper proposes a design of TRBG model based on double-scroll attractors circuits with GST memristor . After implementation and simulation of the chaotic circuit with GST memristor emulator , the chaotic beha vior of the output voltage and inductor current were received. Moreo ver , their dependence on the input voltage revealed the close to double-scroll form. The randomness generated from the proposed circuit was tested by recei ving Fast Fourier T ransform (FFT) and L yapunov exponents of the output voltage. I . I N T R O D U C T I O N T HE Random Number Generator (RNG) is widely used subject in various technology spheres. Thus, it is one of the dominant tools in cryptographic security today and its im- portance gradually rises with the technological development. There are many different techniques to create RNGs based on their classification: true random number generator (TRNG), pseudo random number generator and hybrid number genera- tor . As TRNG is generated from natural/non-deterministic and chaotic sources, its randomness seed can be considered as the most unpredictable and consequently most secured. One ex- ample of the non-deterministic source is the chaotic oscillator which generates double-scroll attractors [1], [2]. This chaotic oscillator is modeled by analogy of the circuit implemented by Chua in 1971, which is essentially oscillator with non-linear resistor for ex ecuting chaotic behavior inside [3]. Moreover , relativ ely new and full of potential memristiv e technology allows to replace non-linear resistor in the proposed chaotic circuit for TRNG because of its non-linear and distinctiv e elec- trical properties. Memristors are differed from each other and classified according to the technology of creation, materials and related features. In this paper we propose a design of TRNG circuit that is based on Phase- Change Memory device ( Ge 2 S b 2 T e 2 ), which is known as GST memristor [4], [5], [6], [7]. F or the present time there is no existing GST memristor model, that is why its characteristical equations and parameters should be in vestigated in order to create its emulator circuit. GST memristor emulator circuit is based on the dif ferent resistance le vels. According to Li et al., the emulator can be constructed from the three serial resistors with different values and parallel to them two capacitors. In order to rev eal the effect of the addition of GST memristor emulator circuit, the theoretically and practically confirmed Chua’ s circuit with non-linear resistor implemented as two diodes with different polarities and two pairs of resistors with different values should be also constructed [8], simulated and compared with studying circuit. This paper is organized as follows. W e first in vestigate the properties of GST memristor and construct its emulator circuit in L TSpice software. Then, mathematical calculations and analysis for GST memristor and other devices parameters are performed. After that, we analyze and compare the orig- inal Chuas circuit with two diodes and the modified circuit with GST memristor model in order to receiv e double-scroll attractors and re veal the most ef ficient one. I I . G S T M E M R I S T O R E M U L A T O R C I R C U I T The chaotic circuit constructed in this paper is based on the fundamental Chua’ s circuit with non-linear resistor implemen- tation. Initially , as it was proposed by K ennedy [8], the original circuit with non-linear resistor , which is implemented with two diodes with different polarities and two pairs of resistors of 3.3 k Ω and 47k Ω values, and negati ve resistor, which consists of operational amplifier and three resistors of 290 Ω , 290 Ω and 1.2k Ω v alues, is constructed. The designed original circuit is demonstrated on the Fig. 1. Fig. 1. Chua circuit with two diodes and resistors implementing non-linear resistor behavior[8] In order to implement new modified Chua’ s circuit with GST memristor , the GST memristor’ s emulator circuit with 2 3 different lev els resistors and two capacitors was constructed because there is no already designed model of GST memristor . As it was suggested by Li et al. [9], the emulator circuit consisting of contact resistor of the electrodes R s serially connected to parallel connection of pure resistor and capacitor of GST ( R p and C p ). In order to better represent equiv alent behavior of the GST memristor two main sources of defect in crystalline grain and at grain boundaries should be considered. That is why , R p and C p are separated to R g and C g and R g b and C g b , that corresponds to the first and second types of defects. The corresponding circuit of the GST memristor emulator can be observed on the Fig. 2. Fig. 2. GST memristor emulator circuit Thus, replacement of the non-linear resistor from the orig- inal circuit with the GST memristor emulator shown on the Fig. 2 leads to the design of the new Chua’ s circuit with GST memristor emulator, as it can be seen from the Fig. 3. Fig. 3. Chua circuit with implemented GST memristor emulator circuit I I I . M AT H E M A T I C A L A NA LY S I S The mathematical analysis of the new chaotic circuit with the GST memristor emulator starts from revealing charac- teristic equations of the main device in the circuit - GST memristor emulator . The relationship between all components of the emulator circuit, which were described in the previous section, can be characterized by following equation for the total impedance of the circuit: Z = R s + R g 1 + j w R g C g + R g b 1 + j w R g b C g b (1) Based on the Eq. (1) generally the memristor emulator circuit was constructed (Fig. 2) and the corresponding values were selected, which will be discussed in the discussion section. Other important equations for characterization of the GST memristor were described by the Xiao et el. [10], the char- acteristic equations for the GST memristor are [11]: lI = M − 1 V M (2) M = f ( V M )[ θ ( V M ) θ ( M R 1 − 1)+ θ ( − V M ) θ (1 − M R 2 )] × γ (1+ W ) (3) f ( V ) = − β V + β − α 2 ( | V + V L | − | V − V R | + V R − V L ) (4) W = W × φ ( W )( W − W t ) (5) Here, V M and I are voltage and current passing through the memristor , M and W represents memristance and phase of GST , and V L and V R are threshold voltages. θ () is the unit step function which limits memristance to the R 1 and R 2 values. Also, α and β are characteristic rates of change of memristor , depending whether V M is less or greater than threshold voltage, respecti vely . Moreover , γ is the correction factor for the variation of memristance because of phase transition, while W t is the threshold of phase transition and φ (W) is the mapping function of phase. The nature of these equations is still under the study . Secondly , it is important to analyze the total chaotic circuit. After analysis of the chaotic circuit with HP memristor by Muthuswamy [13], the following characteristic differential equations for the circuit components without considering memristor effects were derived by him: dφ dt = V 1 ( t ) (6) dV 1 dt = 1 C 1 × [ V 2 − V 1 R 1 − i ( t )] (7) dV 2 dt = 1 C 2 × [ V 1 − V 2 R 1 − i L ( t )] (8) di L dt = V 2 L (9) T aking into the account the memristor effect and using the abov e four equations the nonlinearity equation of the charge in chaotic circuit was deriv ed and taken as cubic [13]: q = θ φ + σφ 3 (10) From the Eq. 10 the next one for memductance can be deriv ed using deriv ativ es: W ( φ ) = dq dφ = θ + σ φ 2 (11) 3 All the above equation can be related to our chaotic circuit with GST memristor, as the circuit is close to ours. All components from the HP memristor’ s emulator circuit can be generally compared with the components of GST memristor’ s emulator circuit. Therefore, θ and σ values, which are con- stants from the Eq. 10 and Eq. 11, for GST memristor emulator circuit can be characterized with the following equations: α = − 1 R load (12) β = 1 3 ( R g + R g b R g b ∗ R load ∗ R c ) (13) Another important part of the chaotic circuit that must be analyzed is the negativ e resistor . In order to mathematically analyze the negati ve resistor circuit, which is designed with operational amplifier and three resistors (see Fig. 3), it is necessary to provide the small-signal analysis. Small-signal analysis is the method to express behavior of non-linear device in terms of linear equations. As it can be seen from the Fig. 4, the operational amplifier was replaced by voltage controlled voltage source, input and output resistors, which is basically the small-signal model circuit. Fig. 4. Chua circuit with implemented GST memristor emulator circuit and small-signal circuit for operational amplifier in the Negativ e Resistor Parametric equations for the circuit on the Fig. 4 can be deriv ed by analyzing it in the follo wing way . Let the opera- tional amplifier be considered as an ideal one. It means, that resistors r in and r out , which are parameters inside operational amplifier , are equal to infinity and zero v alues. Thus, during the analysis r in is replaced by open- circuit notation and rout with short-circuit. In order to properly deriv e equations of small-signal circuit, it should be considered more specifically as on the Fig. 5. First of all, the equation for resistance of the input source R in should be calculated. Fig. 5. Small-signal model for operational amplifier in Negativ e Resistor with open-circuited input resistance and short-circuited output resistance From the nodal analysis of the circuit on the Fig. 5, it is clear that v oltage at the node V+ represented by Eq. (14): V + = V out i ∗ R plus = V out V s (14) Where Vs is the voltage supplied by the source, in this case sinusoidal signal connected with memristor , and it is completely equal to the i × R plus because of infinitely large r in . And V out is the output voltage of the operational-amplifier . On the other side of the open-circuit part the following equation at the node V - using V oltage divider principle can be deriv ed: V − = V out R minus R minus + R load (15) Due to the open circuit between V+ and V -, they can be considered as equal. Equalization of Eq. (14) and Eq. (15) leads to the following: V out − V s = V out R minus R minus + R load (16) Deriv ation of V out from the: V out = V s (1 + R minus R load ) (17) In order to find input current i, the nodes V+ and V out should be considered. As R plus is the positive feedback resistance, input current goes from V s to V out through it: i = V s − V out R plus = V s − V s (1 + R minus R load ) R plus = − V s ∗ R minus R plus ∗ R load (18) Consequently , resistance of the input source R in is calculated simply by di vision of V s to (18). V out = V s − V s ∗ R minus R plus ∗ R load = − R plus ∗ R load R minus (19) Hence, input resistance of the negati ve resistor circuit has negati ve value. Secondly , the equation for the output resistance of the neg- ativ e resistor circuit should be calculated. In order to find it 4 out, open circuit output voltage and short circuit current are required. Open circuit voltage can be calculated by considering node V out with r in = ∞ and r out = 0 conditions and using voltage divider technique. V out = A ( V + − V − ) R load + R minus R load + R minus + r out (20) Inserting equations (14) and (15) in (20): V out = A ( V out − V s − V out R minus R minus + R load ) R load + R minus R load + R minus + r out (21) After manipulations and solving for V out the following equa- tion is recei ved: V out = AV s ( R load + R minus ) R load (1 − A ) + R minus + r out = V oc (22) Then, in order to find short-circuited current i sc the circuit on the Fig. 6 has to be analyzed. Fig. 6. Small-signal model for operational amplifier in Negativ e Resistor with open-circuited input resistance According to the Fig. 6, when the node V out is short- circuited, V out =0, the V - also becomes 0, as it was derived in (15). Therefore, the following equation is receiv ed after KCL technique: i sc = AV s r out + i = AV s r out + V s R plus = V s ( A r out + 1 R plus ) (23) Finally , the division of (22) by (23) results in the following R out equation: R out = V oc i sc = AV s ( R load + R minus ) r out R plus ( AR plus + r out )( R load (1 − A ) + R minus + r out ) (24) Considering the fact, that usually A >> 1 (large numbers) equation (24) can be approximated as: R out = − ( R load + R minus ) ∗ r out ∗ R plus A ∗ R plus ∗ R load (25) I V . S I M U L A T I O N R E S U LT S The simulation of this circuit with GST memristor emulator was done on the L TSpice software and the following results were received: Fig. 7. The Transient characteristic of output V oltage ( V 1 ) Fig. 8. The current of inductor I L and input voltage V 2 characteristic Fig. 9. The output voltage V 1 and input voltage V 2 characteristic 5 Fig. 10. The Fast Fourier Transform of output voltage V 2 Fig. 11. Power of the chaotic circuit with GST memristor emulator circuit implemented with resistors and capacitors The constructed with GST memristor emulator Chua cir- cuit has visually chaotic behavior for the voltage transient characteristic, as it can be seen from the Fig. 7. In order to demonstrate the randomness of the signal spectra, the FFT of output voltage was performed, as it can be seen on the Fig. 10. The significant variations in amplitude corresponding to different frequency values prov e the randomness of the signal. Ho wever , the relationship of inductor current with input voltage and input-output voltages relationship plots do not hav e perfectly corresponding to theory double-scroll forms, but generally resembling double scrolls with chaotic relations with each other (Figs. 8-9). The power across the each component of GST memristor emulator circuit was found from the simulation and its po wer/time dependence across op-amp is shown on the Fig. 11. V . D I S C U S S I O N In this paper we demonstrate the simulation for the Chua’ s original chaotic circuit with non-linear resistor consisting of diodes and resistors together with modified circuit with GST memristor emulator circuit. This section aims to compare results of both circuits in order to rev eal the effect of the memristor addition to the circuit. A. F ast F ourier T ransform First of all, as it can be concluded from Fig. 10, where FFT of output v oltage signals is illustrated, generally the output signal can be counted as random. As it was revealed during the research, the peak amplitude values for the original circuit attain approximately 600, while for the memristiv e circuit it reaches 700. Hence, deviations in voltage values for original circuit smaller than for circuit with memristor emulator , therefore the circuit with GST memristor emulator can be counted as better in terms of chaos. B. P ower analysis Secondly , the general comparison of both circuits powers can be done in the following way . The original circuit requires 9V v alue for V cc and V ee for generating best chaotic output, while modified circuit requires only 3V . It means that second circuit has approximately 3 times less power dissipation. How- ev er , the real analysis rev ealed the following result. According to average calculation of data from each component in non- linear circuit of original chaotic Chua circuit the power is 5.02 mW . While the calculation of av erage power of each component in GST memristor emulator circuit of new chaotic Chua circuit gav e 4.47 mW . It can be concluded, that the less power consumption of the Chua circuit with GST emulator is prov ed and the difference between it and the original circuit’ s power is 0.55 mW . Also, from the Fig. 11 it can be visually seen that power in the circuit with GST memristor varies from about 1.20 mW to 1.80 mW , whereas in original circuit it varies from approximately 4 mW to 26 mW . In spite of receiving small v ariations in v alues, lo w po wer consumption of the circuit with GST memristor emulator is still big advantage. C. Ar ea analysis Thirdly , another important comparison parameter is the area calculation. In order to calculate area of the original chaotic circuit with non-linear resistor circuit, the standard values of areas for diodes and resistors are taken. Diode 1N4148 dimensions are: 3.4 × 1.75 mm 2 for the cathode and 25.4x0.55 mm 2 for wires. Regular chip resistor dimensions are 0.6 × 0.3 mm 2 . In total, the are of about 162 mm 2 will be occupied by the Chua circuit with non-linear resistor consisting of two different polarities diodes and resistors. For the chaotic circuit with GST memristor, assuming that the designed GST memristor model will be used, the total occupied area is assumed to be about 1x1 um 2 , where the GST layer thickness is 150 nm, and for the electrodes is 100 nm, according to Li et al [9]. Hence, the area for the GST memristor model 162000 times smaller than the area for the non-linear resistor . If the emulator circuit is considered, standard dimensions for the chip capacitor are 0.51 × 0.25 mm 2 . The overall area occupied by GST emulator circuit is approximately 1.155 mm 2 , which is still 140 times lesser than the area of the non-linear resistor . Thus, in terms of area parameter it is pro ved that the adv antage on the chaotic circuit with GST memristor side. 6 Fig. 12. L yapunov Exponents from the chaotic circuit with GST memristor emulator with corresponding R g = 25.9k Ω . C g =30.6pF , R gb = 280 Ω and C gb =5pF parameters D. L yapunov exponents randomness test Moreov er , in order to better understand randomness in the constructed circuit, the L yapunov exponents were generated in MatLab software. Corresponding θ and σ values for the characteristic memductance equation of the memristor circuit calculated by Eq. 12 and Eq. 13, are 0.4 × 10 − 3 and 1.35 × 10 − 6 respectiv ely . The L yapunov exponents for the recei ved σ and θ parameters are shown on the Fig. 12. As it can be seen from the Fig. 12, there are two exponents that have similar pic v alues 4 but with different signs at the beginning. After few time firstly positiv e exponent (purple color) becomes negati ve and stable, while firstly negativ e exponent (yellow color) becomes fluctuating around x axis. Generally , both exponents are in close agreement and their sum (red color) is fluctuating negati ve exponent, which prov es presence of the chaos in the circuit [13]. E. V alues of components Finally , the values of used parameters for the GST mem- ristor emulator circuit are R s =100 Ω , R g =25.9k Ω , R g b =280 Ω , as it is recommended in Li et al. [9], and capacitors values as C g =5 pF and C g b =30.6 pF are selected, as it is recommended by Li et al.[12]. P arameters for the rest circuit general elements are: R 1 =2k Ω , C 2 =100nF , C 1 =10nF , L 1 =18mH, R plus =250 Ω , R minus =230 Ω and R load =2.5k Ω . Also, sinusoidal voltage source with 1kHz frequency and 11V amplitude is connected to memristor emulator circuit part. The variations of general elements in the circuit significantly influence on the output. That is why , these parameters are most appropriate to be used. On the same time, variations of GST memristor emulator parameters do not provide visual differences in the output. Howe ver , when the R g value is changed from 25.9k Ω to 40.9k Ω , the corresponding output data were collected and their difference was observed and plotted. As it can be observed from the Fig. 13, dif ference between voltage values for differ - ent resistances is also chaotic and achie ves the maximum of approximately 2 times and minimum of close to 0. Thus, as the change is highly variable, it is difficult to observe it in the output of the chaotic circuit. Fig. 13. Difference of v oltages corresponding to R g =25.9k Ω and R g =40.9k Ω V I . C O N C L U S I O N This paper aimed to show that chaotic behavior can be achiev ed from the Chua’ s oscillator circuit with GST mem- ristor emulator . After construction and simulation on L TSpice software of the original Chua’ s circuit with two diodes of different polarities and two pairs of dif ferent lev el resistors, which implements non-linear resistor functions, and of the modified Chua’ s circuit with GST memristor emulator cir- cuit results were receiv ed and compared. The chaotic output from the targeted memristiv e circuit was obtained, which is the expected result. De viations in amplitude of randomness according to FFT for the new circuit to about 100 greater than in original circuit. Also, comparison in terms of area and power indicates the advantage of the Chua circuit with GST memristor emulator circuit. Additionally , L yapuno v e x- ponents randomness test proved the presence of the chaos in the ne w Chua’ s circuit with GST memristor emulator . More in vestigations of memristor emulator circuit and its parameters analysis are needed. It is recommended to study the addition of GST memristor emulator circuit to the chaotic circuits which generates N-scroll attractors, in order to receive more chaotic behavior . R E F E R E N C E S [1] M. Y aln, J. Suykens and J. V andewalle, True Random Bit Generation F r om a Double-Scr oll Attractor , IEEE TRANSA CTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR P APERS,vol. 51, num. 7. IEEE, July 2004 [Online]. DOI: 10.1109/TCSI.2004.830683 [2] F . Cao and F . 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