Thyristor Voltage Equalizing Network for Crowbar Application

Th yristor V oltage Equalizing Netw ork f or Cr owbar Application ”This paper is a preprint of a paper accepted by IET Po wer Electronics and is subject to Institution of Engineering and T echnology Copyright. When the final version is published, the cop y of record will be a v ailable at IET Digital Library” ∗ Subhash Joshi T . G. 1** and V inod John 2 1 Po wer Electronics Group, Centre for De velopment of Adv anced Computing, Thiruv ananthapuram, India 2 Department of Electrical Engineering, Indian Institute of Science, Bangalore, India Email:vjohn@ee.iisc.ernet.in ** subhashj@cdac.in Abstract: Man y high v oltage applications are realized with series connected thyristors. V oltage imbalance among series connected thyristors during steady state as well as in transients is one of the major concerns. This voltage imbalance is mitigated by using static and dynamic balancing network. Dynamic balancing networks are typically designed based on re verse reco v ery charge of the thyristor during turn-off, which suits many applications. But this is not the case for a crowbar application, where turn-of f of the thyristor is not a major circuit constraint. This paper proposes the design method for dynamic balancing network considering gate turn-on delay time and the balanc- ing network component tolerances. The paper deriv es two models for the dynamic balancing net- work based on its charge-dischar ge c ycle. The importance of charge-dischar ge cycle in the design of dynamic balancing network during high di/dt operation is emphasized. Influence of dynamic balancing resistance and crowbar current limiting inductance on voltage imbalance, charging cur- rent and discharging current is studied using the analytical model. The proposed design method also offers flexibility to incorporate differences in propagation delays among the thyristor driv ers that are used to trigger indi vidual thyristors. Such delays cannot be directly incorporated in the con ventional balancing network design method based on rev erse recov ery . Further , it is also an- alytically shown that designing the dynamic balancing network based on rev erse recov ery charge makes the balancing network lossy and bulk y for crowbar application. Simulation studies and ex- perimental results on a 12 k V , 1 k A cro wbar consisting of six series connected thyristors confirms the theoretical analysis and v alidates the proposed approach for cro wbar applications. Nomenclature R s , a R Static balancing resistance and its tolerance. R d , C d Dynamic balancing resistance and capacitance. a c T olerance of dynamic balancing capacitor . ∗ ”This paper is a preprint of a paper accepted by IET Power Electronics and is subject to Institution of Engineering and T echnology Copyright. When the final version is published, the copy of record will be a v ailable at IET Digital Library” 1 L di/dt limiting inductor of cro wbar . N Number of thyristors connected in series. v G , i G Thyristor gate to cathode v oltage and gate current. v AK , i A Thyristor anode to cathode v oltage and anode current. v AK,N N th thyristor anode to cathode v oltage. V AK, 1 max Maximum voltage across th yristor T 1 during triggering of T 2 to T N . v C d ,L V oltage across the first thyristor and L . V s Operating dc voltage of cro wbar . t dmax , t dmin Maximum and minimum turn on delay time. t dT ol t dmax − t dmin t on T ime tak en by v AK to drop from 100% of forward blocking v oltage to 0 V . i ch , i dis Charging and dischar ging current of dynamic balancing netw ork. I ch max , I dis max Maximum charging and dischar ging current of dynamic balancing netw ork. 1. Introduction An increasing number of power electronic systems are being used in high voltage applications, such as high po wer driv es, high v oltage un-interruptable po wer supply , pulse power systems, static V AR compensator and cro wbar switches [1]. Among the various semiconductor de vices av ailable for design, thyristor is widely used in v arious po wer electronic systems when the operating volt- ages are in the range of kilov olts. A vailability of thyristors at higher voltage and current rating makes thyristor a good choice for such applications. In many high voltage applications, meeting the required voltage rating with single thyristor is not feasible. Hence, there is a need for series connection of the thyristor switches [2]. A cro wbar is a fault energy-di verting element built with thyristors, connected at the output of high voltage dc source as shown in Fig. 1(a). The dc source feeds po wer to sensitiv e loads, like micro wa v e or plasma tubes. The triggering of cro wbar is initiated by turning on the thyristors when a fault signal is receiv ed from fault sensing circuits in the load. This can be for conditions of ov er voltage, or short circuit, or any other situations which activ ate the protection circuits. When the cro wbar receiv es the trigger signal from a protection circuit, all the series connected thyristors are turned-on and fault energy , from the storage devices such as capacitors and the follo w-on current from the input power supply , is div erted through crowbar within a fe w microseconds. Concurrent to this, the trigger signal is also transmitted to open the input circuit breaker (CB). The cro wbar is kept ON until the input CB opens, which can take as long as 100 ms . This along with the triggering of the cro wbar reduces the dc v oltage close to zero [3]. While connecting thyristors in series, sharing of voltage by each thyristor during steady state as well as in dynamic condition is one of the major concerns to be addressed [4]. The main cause of voltage imbalance in series connected thyristors during steady state is due to their dif ference in rev erse blocking leakage current. If the V -I characteristics of thyristors connected in series are dif ferent, for the same leakage current, the voltage sharing among thyristors will be unequal as illustrated in Fig. 2(a). Passiv e resistors R s called static balancing networks are connected across each thyristor as shown in Fig. 1(b) as a solution for static voltage imbalance. The value of R s is selected based on the re verse leakage current of th yristor [5]. When series connected thyristors are turned-off transient voltage imbalances can occur among them due to mismatch in their re verse reco very charge [6]. When the thyristor is turned-off, the charge carriers stored in the de vice need to be remov ed completely before it recov ers its voltage blocking capability [7, 8]. The difference in the amount of charge stored in the junction makes 2 (a) (b) (c) (d) F ig. 1 . Schematic of cr owbar cir cuit showing a. Po wer supply and load connection at dc output. b . Static and dynamic balancing network. c. Simplified equiv alent circuit when thyristor T 1 is of f and other ( N − 1) thyristors are triggered on initially . d. Simplified equi v alent circuit when thyristor T 1 is turned on subsequently . the turn of f time to vary from one thyristor to another as illustrated in Fig. 2(b). Passi v e resistor- capacitor network ( R d , C d ), sho wn in Fig. 1(b), called dynamic balancing network, is used as a solution for transient voltage imbalance. These are designed based on the mismatch in re verse recov ery char ge of the thyristors [9]. Con ventionally the static and dynamic balancing networks are designed by considering two modes of operation of thyristors [10, 11]; in mode 1, thyristors are in blocking stage and in mode 2, thyristors are being turned-of f. These modes of operation of the thyristors reflect actual operat- ing conditions in most applications. Hence in many literature the balancing network are designed considering turn-off condition also [12, 13, 14]. But this is not true in case of crowbar operation, where in mode 1, thyristors are in forward blocking stage and in mode 2, thyristors are being turned-on. This is shown to require new constraints for selection of the static and dynamic bal- 3 (a) (b) 5 10 15 1.0 1.5 2.0 2.5 V G (V) V AK (kV) V A K (approximated) 0 0.0 0.5 0 5 10 15 20 time ( μ s) t d t on t s (c) F ig. 2 . Characteristics showing a. Mismatch in two thyristor V -I characteristics. b . Mismatch in two thyristor rev erse reco very characteristics. c. v AK and v G wa v eforms sho wing turn-on characteristics of thyristor measured in the laboratory . ancing network components. In [15], switching-on ov er voltage across series connected thyristor is discussed, b ut the ov er voltage addressed is due to the firing capacitor connected across gate and cathode. For a three-phase bridge circuit, the turn-on ov er voltage during commutation of the complementary switch is discussed in [16], but the o v er v oltage is solved numerically only . When series connected thyristors are turned-on, voltage imbalance can occur due to dif ference in gate turn-on delay time. In [17], the design of a dynamic balancing network based on gate turn-on delay time is addressed. The analysis detailed in [17] did not consider the influence of dy- namic balancing resistance and the crowbar current limiting inductance. In this paper the analysis is extended by considering the influence of dynamic balancing resistance. The paper deriv es two models for the dynamic balancing network based on its charge-dischar ge cycle. The importance of charge-dischar ge cycle in the design of dynamic balancing network during high di/dt operation of cro wbar is also emphasized in the paper . Influence of dynamic balancing resistance and cro wbar current limiting inductance on voltage imbalance, char ging current and dischar ging current is also 4 explored. The analysis shows that for high di/dt applications the charging current of dynamic balancing network can be higher than the discharging current. Hence by considering only the dis- charging current as done in the con ventional method, the design leads to large deviations in the results. The paper compares this design with that using traditional dynamic balancing component design based on re verse recov ery charge. It is also found that the proposed design provides flexibil- ity to include the dif ference in propagation delays among the gate dri ver circuits used in triggering indi vidual thyristors. This allows for a design without complex pulse synchronizing circuit used in crowbar applications. T olerances of components are also considered in the proposed balanc- ing network design. The analytical design results are validated using time domain simulations. Experimental results using a laboratory cro wbar prototype confirms the theoretical analysis. 2. Thyristor Characteristics T urn-on time of thyristor can be divided into three parts (a) delay time (b) rise time and (c) con- duction spreading time [18]. After initiating the gate-to-cathode current I G , an appreciable time t d is required to establish the charge in thyristor to support a current greater than its holding cur- rent. During rise time, i A rises rapidly in a small area near the vicinity of the gate and a similar decrease in voltage occurs between anode and cathode v AK . The area of conduction spreads dur - ing spreading time until the whole cathode starts conducting. In many applications, e valuating the delays of i A rise and v AK fall with respect to gate voltage signal is better suited than with respect to gate current signal. Also, while using devices such as Light T riggered Thyristor (L TT) the gate currents are not accessible. In the datasheet t d is defined as the time from start of the triggering pulse v G to v AK dropping below 90% of the applied forward off-state voltage [19], as sho wn in a sample experimental wa v eform gi ven in Fig. 2(c). The time during which v AK drops from 90% to 20% is referred as turn on time, where as during spread time t s , v AK drops from 20% to forward on voltage. Howe v er for the analysis the v ariation of v AK is assumed to be linear as sho wn by dotted line in Fig. 2(c). Such an approximation shows a worst case v AK , since the approximated v AK is delayed more than the actual curve. In the approximated v AK , turn on time t on is redefined as the time taken by v AK to drop from 100% of forward blocking v oltage to 0 V . Thyristors hav- ing smaller t d will turn-on earlier than the one having higher t d . This leads to v oltage imbalance among series connected thyristors. Hence dynamic balancing network consisting of R d and C d , should be designed based on the gate turn-on delay time mismatch of the thyristors used. From the datasheet of thyristors [20], it is found that forward leakage current as well as re verse leakage cur - rent are similar . Hence the method used to design the static balancing network R s remains similar to the con ventional method. Howe v er in the proposed method the worst case balancing network component tolerances is also considered in the design procedure. 3. Proposed design of static and dynamic balancing network Inductor L connected in series with the thyristor shown in Fig. 1(b), ensures that the slope of the current does not cause any damage to the thyristor . The upper limit of the value of this inductor is based on the amount of fault energy that can be tolerated by the load of the cro wbar sho wn in Fig. 1(a). The lower limit of the value of the inductor is based on the di/dt rating of the thyristor . 5 3.1. Charging cycle of dynamic balancing network Let N thyristors connected in series be fed from a dc source, V s , through a di/dt limiting inductor , L , as sho wn in Fig. 1(b). For the dynamic balancing network analysis the following assumptions are made: 1. For worst case analysis the thyristor T 1 is chosen to hav e maximum gate turn-on delay time t dmax and remaining ( N − 1) thyristors ha ve minimum turn-on delay time t dmin . The differ - ence between the maximum and minimum thyristor turn-on delay time is defined as, t dT ol = t dmax − t dmin (1) 2. During the turn-on process of thyristor , anode-to-cathode voltage varies linearly and the curve is identical for all thyristors except it is delayed by its o wn gate turn-on delay time. 3. Influence of the static balancing network R s on dynamic balancing network is assumed to be minimal due to its relati ve high impedance. 4. For the worst case analysis the capacitor connected across the first thyristor is chosen to ha v e the lo west tolerance limit a c where a c is defined as C d ∈ { C d,nominal (1 ± a c ) } The voltage appearing across each thyristor during forward blocking state is V s / N . t on is the time taken by v AK to reach zero from its forward blocking voltage, V s / N . Then the expression for the v ariation of voltage across ( N − 1) thyristors at time t , in the time duration t dmin ≤ t ≤ ( t on + t dmin ) is gi ven by , v AK, 2 ( t ) = v AK, 3 ( t ) = · · · = v AK,N ( t ) = − V s N t on ( t − ( t on + t dmin )) (2) T otal voltage appearing across ( N − 1) thyristor is, v [ AK, 2 to N ] ( t ) = − ( N − 1) V s N t on ( t − ( t on + t dmin )) (3) Since the voltage transition across the first device T 1 is not yet initiated, the dynamic balancing network connected across T 1 will be in charging cycle. During this cycle the voltage appearing across L and T 1 , which includes the balancing network, is sho wn by a simplified equi v alent circuit in Fig. 1(c) and is gi ven by , v C d ,L ( t ) = V s − V [ AK, 2 to N ] ( t ) v C d ,L ( t ) = V s N + V s ( N − 1)( t − t dmin ) N t on (4) Based on the relati ve v alue of t on and t dT ol during this cycle, the v C d ,L ( t ) takes follo wing v alues 1. If t dT ol ≤ t on v C d ,L ( t ) = V s N + V s ( N − 1)( t − t dmin ) N t on (5) 6 2. If t dT ol > t on , the ( N − 1) thyristors turn on transitions will be completed at t = ( t dmin + t on ) . Hence, v C d ,L ( t ) =    V s N + V s ( N − 1)( t − t dmin ) N t on , if t ≤ ( t dmin + t on ) V s , if t > ( t dmin + t on ) (6) Hence the charging cycle of dynamic balancing network include two dynamic models based on relati ve v alue of t on and t dT ol , which are considered belo w . 3.1.1. Dynamic model f or t dT ol ≤ t on : The simplified equiv alent circuit is sho wn in Fig. 1(a) where v C d ,L ( t ) is gi ven by (5). If i ch ( t ) is the charging current of dynamic balancing network, the dynamic equation related to this circuit is gi ven by , L d 2 i ch dt 2 + R d di ch dt + i ch (1 − a c ) C d = V s ( N − 1) N t on (7) The minimum value of tolerance is chosen for C d across thyristor T 1 in (7), as this gi ves the worst case ov er voltage for T 1 . In most crowbar balancing circuits, R d is much smaller than the characteristic impedance leads to complex solutions to (7). At t = t dmin , choosing the initial conditions as i ch ( t ) = 0 and voltage across the inductor is zero, the above dynamic equation can be solved as, i ch ( t ) = V s ( N − 1)(1 − a c ) C d N t on " 1 − e − δ ( t − t dmin ) ω d p L (1 − a c ) C d cos ( ω d ( t − t dmin ) − φ ) # (8) where, δ = R d 2 L , ω d = s 1 L (1 − a c ) C d −  R d 2 L  2 and φ = tan − 1  δ ω d  . Therefore, the voltage appearing across the first de vice is giv en by , v AK, 1 ( t ) = V s N + V s ( N − 1) N t on  ( t − t dmin ) − e − δ ( t − t dmin ) ω d sin ( ω d ( t − t dmin ))  (9) The second term in (9) represents the transient term initiated after triggering ( N − 1) thyristors. Since the first thyristor T 1 get triggered at t = t dmax , the maximum v alue of i ch ( t ) and V AK, 1 ( t ) are obtained by choosing t = t dmax in (8) and (9) respecti vely gi ven by , I ch max = V s ( N − 1)(1 − a c ) C d N t on " 1 − e − δ t dT ol ω d p L (1 − a c ) C d cos ( ω d t dT ol − φ ) # (10) V AK, 1 max = V s N + V s ( N − 1) N t on  t dT ol − e − δ t dT ol ω d sin ( ω d t dT ol )  (11) 7 3.1.2. Dynamic model f or t dT ol > t on : Let t 1 be defined as ( t on + t dmin ) . For t ≤ t 1 , v C d ,L ( t ) hold the first condition of (6) and the solutions are gi ven in (8) and (9). For t > t 1 , v C d ,L ( t ) is gi ven by the second condition of (6) and the dynamic equation can be expressed as, L d 2 i ch dt 2 + R d di ch dt + i ch (1 − a c ) C d = 0 (12) This can be solved by applying initial conditions (a) i ch ( t ) at t = t 1 from (8) denoted as I ch ( t 1 ) and (b) voltage across C d at t 1 denoted by V c ( t 1 ) obtained as  V AK, 1( t 1 ) − I ch ( t 1 ) R d  . V AK, 1( t 1 ) is giv en by V AK, 1 ( t ) at t = t 1 obtained from (9). The solution of (12) is, i ch ( t ) = e − δ ( t − t 1 ) [ K 1 cos ( ω d ( t − t 1 )) + K 2 sin ( ω d ( t − t 1 ))] (13) where, K 1 = I ch ( t 1 ) and K 2 = V s − V c ( t 1 ) − I ch ( t 1 ) Lδ Lω d . Therefore, the voltage appearing across the first de vice is giv en by , V AK, 1 ( t ) = V s + Le − δ ( t − t 1 )  ( K 1 ω d + K 2 δ ) sin ( ω d ( t − t 1 ))+ ( K 1 δ − K 2 ω d ) cos ( ω d ( t − t 1 ))  (14) The maximum v alue of i ch ( t ) and V AK, 1 ( t ) during this mode of operation can be obtained by choosing t = t dmax in (13) and (14) respecti vely . 3.2. Discharging cycle of dynamic balancing network When thyristor T 1 is turned on at t = t dmax , C d discharges into the thyristor shown by a simplified equi v alent circuit gi ven in Fig. 1(d). The slope of v AK of first thyristor is assumed to be same as that of ( N − 1) thyristors. Then the dynamic equation related to Fig. 1(d) is giv en by , R d di dis dt + i dis (1 − a c ) C d = − V s N t on (15) Depending of the type of model used in (5) and (6) the initial conditions are chosen. The initial condition for i dis ( t ) , denoted by I dis ( t dmax ) , is obtained either from (8) for t dT ol ≤ t on or from (13) for t dT ol > t on by choosing t = t dmax . Using this initial condition the solution to the dynamic equation (15) is gi ven by , i dis ( t ) =  I dis ( t dmax ) + V s (1 − a c ) C d N t on  e − ( t − t dmax ) R d (1 − a c ) C d − V s (1 − a c ) C d N t on (16) As time t increases i dis ( t ) magnitude increases. Hence the maximum value of i dis ( t ) can be obtained when thyristor T 1 is completely turned on. Starting from forward sur ge voltage, due to turn on of ( N − 1) thyristor , the time taken by the first thyristor to reach its forward conduction voltage is, t on, 1 = V AK, 1 max N t on V s + t dmax (17) 8 where V AK, 1 max is obtained either from (9) for t dT ol ≤ t on or from (14) for t dT ol > t on by choosing t = t dmax . The maximum v alue of i dis ( t ) can be obtained by choosing t = t on, 1 in (16) and is given by , I dis max =  I dis ( t dmax ) + V s (1 − a c ) C d N t on  e − ( t on, 1 − t dmax ) R d (1 − a c ) C d − V s (1 − a c ) C d N t on (18) 3.3. Static balancing resistance ( R s ) Design of static balancing network is well established in literature [5][10]. Howe v er , ev en in this case it is important to consider the tolerance of the resistor R s used in the balancing network. The static balancing resistance across each thyristor is gi v en by , R s = V d 1 ( N (1 − a R ) + 2 a R ) − (1 + a R ) V s ( N − 1)(1 − a 2 R )( I Dmax − I Dmin ) (19) where, V d 1 is the maximum allo wable steady state forward blocking voltage across thyristor , I Dmax and I Dmin are the maximum and minimum value of forward leakage current and a R is tolerance limit of selected resistor such that R s ∈ { R s,nominal (1 ± a R ) } . 4. Analysis of charge-discharge cycle of d ynamic balancing network Since many practical thyristor characteristics hav e t dT ol ≤ t on , this section analyses this case in detail. F or the analysis consider a crowbar of 12 k V rating built with 6 thyristor de vices in series and a di/dt limiting inductor of 250 µH . The percentage over voltage appearing across the thyristor T 1 is defined as, V d ov = V d 1 max − ( V s / N ) ( V s / N ) 100 (20) For various v alues of C d , the V d ov , I ch max and I dis max are computed from (20), (10) and (18) respecti vely where V d 1 max is ev aluated using (11). The computation is carried out by choosing t on = 5 µs and k eeping t dT ol of thyristor and R d as parameters. The curve V d ov versus C d is plotted in Fig. 3(a) for three different t dT ol such as 3 µs , 2 µs and 1 µs and R d of 0Ω , 15Ω and 30Ω . Fig. 3(a) sho ws that in all cases, beyond certain v alue of C d there is no significant reduction in V d ov . Also from Figs. 3(b) and (c) higher v alue of C d leads to higher charge I ch max and dischar ge I dis max current. But the influence of C d on discharge current is found to be significant compared to its influence on charging current. Hence by choosing the minimum required value of C d that is suf ficient to meet the required V d ov , the discharge current can be limited to the minimum value. Fig. 3(a) also sho ws an increase in V d ov with resistance R d whereas char ge and dischar ge currents reduces with R d for a gi ven C d . Hence by selecting a minimum value of R d the V d ov can be further reduced pro vided the char ge and discharge currents are within the rating of C d as well as thyristor . For a gi ven C d the V d ov also depends on t dT ol sho wn in Fig. 3(a). F or higher t dT ol the V d ov is higher . Similar characteristics are observ ed for char ging and dischar ging current, which are shown in Figs. 3(b) and (c) respecti vely . Ho we ver the influence of t dT ol on discharge current are found 9 0 20 40 60 80 100 0 2 04 06 08 0 1 0 0 V d_ov Capacitance, C d (nF) 1 t dTol =3 μ s t dTol =2 μ s t dTol =1 μ s 2 3 4 5 6 7 9 8 R d =30 Ω fo r , , R d =0 Ω fo r , , 3 6 9 R d =15 Ω for , , 1 4 7 2 5 8 (a) 0 10 20 30 40 0 2 04 06 08 0 1 0 0 I ch_max (A) Capacitance, C d (nF) 1 t dTol =3 μ s t dTol =2 μ s t dTol =1 μ s 5 9 2 3 4 6 7 8 10 11 12 R d =30 Ω fo r , , R d =0 Ω fo r , , 3 7 11 R d =15 Ω fo r , , 1 5 9 2 6 1 0 R d =100 Ω fo r , , 4 8 1 2 (b) -40 -30 -20 -10 0 0 20 40 60 80 100 I dis_max (A) Capacitance, C d (nF) R d =100 Ω R d =30 Ω R d =0 Ω & 15 Ω 1 2 3 4 5 6 7 8 9 10 11 12 t dTol =3 μ s for , , , t dTol =1 μ sf o r , , , 3 6 9 t dTol =2 μ sf o r , , , 1 4 7 2 5 8 1 2 1 0 11 (c) F ig. 3 . V ariation in the thyristor peak str ess with C d for differ ent t dT ol and R d , with t on = 5 µs a. Percentage of ov er v oltage V d ov . b . Maximum charging current I ch max . c. Maximum discharging current I dis max . 10 0 20 40 60 80 100 0 2 04 06 08 0 1 0 0 V d_ov Capacitance, C d (nF) t dTol =3 μ s t dTol =2 μ s t dTol =1 μ s 1 2 3 4 5 6 7 8 9 t on =10 μ s for , , 3 6 9 t on =7.5 μ s for , , 2 5 8 t on =5.0 μ s for , , 1 4 7 (a) 0 10 20 30 40 0 2 04 06 08 0 1 0 0 I ch_max (A) Capacitance, C d (nF) t dTol =3 μ s t dTol =2 μ s t dTol =1 μ s 1 2 3 4 5 6 7 8 9 t on =10 μ s for , , 3 6 9 t on =7.5 μ s for , , 2 5 8 t on =5.0 μ s for , , 1 4 7 (b) -40 -30 -20 -10 0 0 20 40 60 80 100 I dis_max (A) Capacitance, C d (nF) t on =10 μ s t on =7.5 μ s t on =5 μ s 1 2 3 4 5 6 7 8 9 t dTol =3 μ sf o r , , t d Tol =1 μ s for , , 3 6 9 t dTol =2 μ s for , , 1 4 7 2 5 8 (c) 0 5 10 0 2 04 06 08 0 1 0 0 I ratio Capacitance, C d (nF) t dTol =3 μ s t dTol =2 μ s t dTol =1 μ s 1 2 3 4 5 6 7 8 9 t on =10 μ s for , , 3 6 9 t on =7.5 μ s for , , 2 5 8 t on =5.0 μ s for , , 1 4 7 (d) F ig. 4 . V ariation in the following parameter s with C d for differ ent t dT ol and t on keeping R d = 5Ω a. Percentage of ov er v oltage V d ov . b . Maximum charging current I ch max . c. Maximum discharging current I dis max . d. Ratio of I ch max and I dis max . to be minimal for smaller values of R d . Figs. 4(a), (b) and (c) shows the influence of t on on V d ov , I ch max and I dis max for R d = 5Ω . These curves are plotted for three dif ferent t dT ol such as 3 µs , 2 µs and 1 µs and t on of 5 µs , 7 . 5 µs and 10 µs . The V d ov , I ch max and I dis max are highly influenced by t on and increases when t on reduces for a giv en C d . The rate of increase in V d ov , I ch max and I dis max for dif ferent t on is more when the ratio between t on and t dT ol is less. I ratio = I ch max /I dis max for dif ferent C d and R d = 5Ω is shown in Fig. 4(d). The curves are plotted for three dif ferent t dT ol such as 3 µs , 2 µs and 1 µs and t on of 5 µs , 7 . 5 µs and 10 µs . From Fig. 4(d) it can be observed that I ratio is approximately independent of t on . Also for lower C d from Fig. 4(d) the charging current is higher than the discharging current. Hence for the design of dynamic balancing network C d , it is necessary to compute both charging or dischar ging current. The influence of L on V d ov , I ch max and I dis max are shown in Figs. 5(a) and (b) respecti vely . For a gi v en C d as L increases V d ov and I ch max reduces whereas I dis max is independent of L . Hence for high di/dt applications char ging current can be higher than the dischar ging current. This sho ws the importance of dynamic balancing netw ork when operating the cro wbar at high 11 0 20 40 60 80 100 0 2 04 06 08 0 1 0 0 V d_ov Capacitance, C d (nF) t dTol =3 μ s t dTol =2 μ s t dTol =1 μ s 1 2 3 4 5 6 L=125 μ H for , , L=250 μ H for , , 1 3 5 2 4 6 (a) -45 -30 -15 0 15 30 45 60 75 0 20 40 60 80 100 I dis_max (A) I ch_max (A) Capacitance, C d (nF) t dTol =3 μ s t dTol =2 μ s t dTol =1 μ s 1 2 3 4 5 6 t dTol =3 μ s, 2 μ s, 1 μ s L=125 μ H, 250 μ H L=125 μ H for , , L=250 μ H for , , 1 3 5 2 4 6 (b) F ig. 5 . V ariation in the circuit performance factors with C d , for dif fer ent t dT ol and L , keeping R d = 5Ω and t on = 5 µs a. Percentage of ov er v oltage V d ov . b . I ch max (positi ve polarity) and I dis max (negati ve polarity). di/dt and importance of considering both currents for its design. 4.1. Selection of dynamic balancing networ k ( R d , C d ) From the analysis for a giv en set of conditions V d ov sho ws minimum value for R d = 0 . Hence to start, C d is computed for the maximum allowable transient v oltage V d 1 max from (11) keeping R d = 0 . From the computed C d the I ch max and I dis max are calculated for R d = 0 from (10) and (18) respecti vely . If these currents are within the acceptable limit then dynamic balancing network will have only C d of the computed v alue. If either I ch max or I dis max is higher than the specified v alue then from Figs. 3(b) and (c) the choice is to either increase R d or reduce C d by compromising on the required V d ov . If significant increase of R d is required to bring I ch max and I dis max within limit, then reducing C d will be preferable approach. The other parameters V s , N and L required for the computation are kno wn from the crowbar circuit and t dmax , t dmin and t on can be obtained from the selected thyristor datasheet. 5. Simulation results From the system specification, the dc v oltage rating of crowbar is 12kV . By connecting 6 thyristors having part number 5STP 03X6500 (ABB) in series the abov e voltage rating can be achiev ed. In nominal operating condition, each thyristor will see a voltage of 2 k V . Other important crowbar design parameters for this thyristor obtained from datasheet are gi v en in T able 1. 5.1. Estimation of dynamic balancing capacitor ( C d ) Choose the maximum allow able over voltage across the thyristor as 50% ( 1 k V ) for a maximum v alue of t on equal to 5 µs and t dT ol of 3 µs . Then from Fig. 3(a) for R d = 0 , the minimum value of C d required to limit V d ov with 50% is 40 nF . Also from Fig. 3(a) with C d of 40 nF , V d ov will be less than 50% if t on is higher than 5 µs and t dT ol less than 3 µs . Since the C d experience 3 k V the 12 T able 1 Parameters of related to crowbar and th yristors Parameters V alues DC source voltage, V s 12 k V Series inductance to crowbar , L 250 µH Rated dc voltage of thyristor , V D ( dc ) 3 . 3 k V Number of thyristor in series, N 6 Max. forward leakage current, I Dmax 350 µA Min. forward leakage current, I Dmin 100 µA Max. turn ON delay time, t dmax 3 µs Min. turn ON delay time, t dmin 0 µs R.M.S. on state current, I T ( rms ) 550 A Peak non-repetitiv e sur ge current, I T S M 4500 A Minimum recov ery charge, Q min 1000 µC Maximum recov ery charge, Q max 2300 µC T olerance limit of capacitor, a C 0 . 1 T olerance limit of resistor, a R 0 . 05 voltage rating of C d is chosen as 4 k V . 5.2. Estimation of dynamic balancing resistor ( R d ) The I ch max and I dis max for t on = 5 µs , t dT ol = 3 µs and R d = 0 is recorded from Figs. 3(b) and (c) respectiv ely . From Fig. 3(b) the I ch max for C d = 40 nF is 33 A whereas from Fig. 3(c) the discharging current 15 A . Since these current are small compared to the current rating of thyristor , gi ven in T able 1, C d , can be directly connected without any current limiting resistor . Ho we ver a small damping resistance of 3Ω is chosen for R d . This is sufficient considering a parasitic loop inductance of the ( R d , C d ) balancing network and thyristor is of the order of 100 nH . 5.3. Estimation of static balancing resistor ( R s ) Based on the parameter gi v en in T able 1 and limiting the maximum steady state v oltage across an y of the thyristor V d 1 to 135% ( 2 . 7 k V ), the R s can be estimated from (19) as 2 . 5 M Ω . Simulations are carried out with estimated values of static and dynamic balancing network elements. In simulation t on and t dT ol is chosen as 5 µs and 3 µs respecti vely . The v oltage wa v eform across each thyristor during turn-on is shown in Fig. 6(a). The char ging and discharging current of C d are shown by positi ve and neg ati ve polarity respecti vely in Fig. 6(b). Simulation results sho ws that the maximum dynamic voltage reaches 3 k V and matches the target design of V d ov of 50% in the analytical design. Also from simulation the I ch max and I dis max through C d is found to be 33 A and 15 A respecti vely that also matches with the analytical design performance from section 5.2. 13 (a) 0 500 1000 1500 2000 2500 3000 3500 VD1 VD2 VD3 VD4 VD5 VD6 0 4e-006 8e-006 1.2e-005 1.6e-005 2e-005 Time (s) 0 -10 -20 10 20 30 40 I(Rd) (b) VD1 VD2 to VD6 i ch ( t ) i dis ( t ) v AK (V) ( A ) (c) V G,T 2 V G,T 1 V AK,T 1 V AK,T 2 V G : 2V/div . V AK : 100V/div . 2 . 5 µs -  (d) V G,T 2 V G,T 1 V AK,T 1 V AK,T 2 V G : 2V/div . V AK : 100V/div . 2 . 5 µs -  F ig. 6 . Simulation waveforms (a. & b .) and experimental waveforms (c. & d.) considering worst case delay a. Simulation results sho wing v oltage across all 6 thyristors, considering worst case delay and parameter tolerance for the first thyristor . b . Simulation results showing char ging i ch ( t ) and discharging i dis ( t ) current of the first thyristor . c. F or t dT ol = 2400 ns , v AK wa v eforms across T 1 and T 2 with respecti v e g ate signals without balancing network. d. For t dT ol = 2400 ns , v AK wa v eforms across T 1 and T 2 with respectiv e gate signals with balancing network. 6. Comparison with dynamic balancing network based on reverse recovery char ge Design of C d based on rev erse recovery charge is reported in [5]. V alue of C d based on rev erse recov ery char ge is, C d =  1 + ( N − 1) 1 − a C 1 + a C  ( Q max − Q min ) (1 − a C )  V d 1  1 + ( N − 1) 1 − a C 1 + a C  − V s  (21) Using data giv en in T able 1 and limiting the same maximum allowable ov er v oltage across thyristor to 50%, the v alue of C d based on re verse reco v ery charge is computed as 2 . 25 µF . From (10) and (18) the I ch max and I dis max for the abov e C d with t dT ol = 3 µs and t on = 5 µs is 36 A and 810 A respecti v ely . Comparison with the v alues obtained from proposed design of dynamic balancing network, the I ch max is comparable where as the I dis max is significantly large, closer to the rating of thyristor giv en in T able 1. T o reduce the discharging current R d of large 14 (a) (1) (2) (3) (b) L Thyristor stack (c) v G,T 1 i dis (t) i ch (t) v AK,1 v AK,2 v G : 2V/div . v AK : 100V/div . i ch : 1A/div . 2 . 5 µs -  (d) Crowbar voltage,V s (2kV/div .) Crowbar current (200A/di v .) 200 µs -  F ig. 7 . Showing a. Photographs of static and dynamic balancing network where the component (1) is C d (2) is R d and (3) is R s . b . Photographs of 12 k V , 1 k A solid state crowbar . c. Char ging (negati ve polarity) and discharging (positi ve polarity) current from dynamic balancing network connected to T 1 along with its gate signal and v oltage wa v eform across T 1 and T 2 . d. Nominal voltage V s ( 10 k V ) applied across crowbar and current ( 1 kA peak ) through cro wbar . v alue of resistance and wattage is required. Comparing the v alues of C d based on turn-on delay time and based on re v erse reco v ery char ge, 15 it is found that C d with rev erse recovery charge is 56 times larger than that of C d obtained with turn-on delay time. By Fig. 3(a) such a large value of C d will not giv e any additional reduction of V d ov , instead it significantly increases the discharging current. This large value of discharging current as well as large v alue of capacitance makes the dynamic balancing network lossy , b ulky as well as costly . 7. Experimental Results Static and dynamic balancing network are fabricated for a crowbar of 12 k V , 1 k A rating. The dy- namic balancing components C d and R d chosen for the e xperiment are 47 nF and 3Ω respectiv ely . The v alue of static balancing resistance R s used is 2 . 2 M Ω . Both static and dynamic balancing net- work required for one thyristor are assembled on a single four layer PCB, where interconnecting tracks are only routed through inner layers. The top and bottom layer provides isolation to the in- ner tracks from external media. The assembled static and dynamic balancing network is shown in Fig. 7(a). These balancing network PCBs are mounted on cro wbar unit as sho wn in Fig. 7(b). The performance of balancing circuit is e valuated in lo wer voltage by choosing 6 numbers of thyristors T 1 to T 6 having similar t dT ol . A known delay is introduced to the gate signal of first thyristor T 1 and the voltages across all six thyristors are recorded with and without the voltage balancing net- work. The experiment is carried out with a dc voltage of 480 V and t dT ol of 800 ns and 2400 ns . The t dT ol of 800 ns emulate the difference in propagation delay among gate signals of thyristors and 2400 ns is typically the maximum difference in turn-on delay time among thyristors. The t on observed for the thyristors used for the experiment is 3 µs . The other parameters are as gi ven in T able 1. The v oltage wa v eforms across the thyristors during turn-on without balancing network for t dT ol = 800 ns are shown in Figs. 8(a) and (b) where Fig. 8(a) are for T 1 and T 2 and Fig. 8(b) are for T 3 to T 6 . An appreciable over voltage of 3 . 75 times its steady state voltage is observ ed across the delayed thyristor T 1 e ven for small value of t dT ol . The effecti veness of balancing network is sho wn in Figs. 8(c) and (d) where Fig. 8(c) are for T 1 and T 2 and Fig. 8(d) are for T 3 , T 4 , T 5 and T 6 . The ov er voltage across T 1 with balancing network is found to be insignificant as shown in Fig. 8(c). The ov er voltage computed analytically with (11) is 82 V which is 2% above its steady state value that is close to the e xperimental result shown in Fig. 8(c). The charging and discharg- ing current of dynamic balancing network is sho wn in Fig. 7(c) measured to be 0 . 2 A and − 1 . 2 A respecti vely where are the respecti ve computed values from (10) and (18) are 0 . 18 A and − 1 . 14 A closely matching with the experimental results. The experiment is repeated with t dT ol = 2400 ns that is close to the maximum v alue mentioned in the thyristor datasheet [20]. The voltage wa veforms across T 1 and T 2 during turn-on without balancing network are shown in Fig. 6(c) where as that of T 3 to T 6 are not shown since they are triggered simultaneously . The over voltage across T 1 is found to be 676 V that is 8 . 45 times that of the steady state v alue of 80 V . The voltage wa v eforms across T 1 and T 2 with balancing network is sho wn in Fig. 6(d) where the ov er v oltage across T 1 is measured to be 112 V that is 1 . 4 times of its steady state value. The computed ov er voltage from (11) is found to be 112 . 6 V which is close to the experimental result and percentage of over voltage is close to the simulation results sho wn in Fig. 6(a). The crowbar is operated by discharging the nominal forward blocking voltage of 10 k V to allo w nominal current of 1 k A . The applied forward voltage and crowbar current are shown in Fig. 7(d). The performance of balancing network and cro wbar are found to be satisfactory and the proposed design procedure for the balancing network is validated with analytical, simulation and experimental results. 16 (a) V G,T 2 V G,T 1 V AK,T 1 V AK,T 2 V G : 2V/div . V AK : 100V/div . (b) V AK,T 3 to V AK,T 6 V AK : 100V/div . (c) V G,T 2 V G,T 1 V AK,T 1 V AK,T 2 V G : 2V/div . V AK : 100V/div . (d) V AK,T 3 to V AK,T 6 V AK : 100V/div . F ig. 8 . F or t dT ol = 800 ns , the v AK waveform acr oss (T ime scale: 2 . 5 µs/div . ) a. T 1 and T 2 with respecti ve g ate signals without balancing network. b . T 3 to T 6 without balancing network. c. T 1 and T 2 with respecti ve g ate signals with balancing network. d. T 3 to T 6 with balancing network . 8. Conclusion V oltage balancing networks are often designed by considering two modes of operation of thyristors which are rev erse blocking mode and turn-of f mode. Since in a cro wbar application, the modes of operation of thyristor are different, the con v entional method used for the design of balancing network if adopted, leads to very bulk y balancing components with higher power loss. This paper proposes a design method for dynamic balancing network based on gate turn-on delay time. The paper deri v es two models for the dynamic balancing network and sho ws its importance in the design of dynamic balancing network when cro wbar operate at high di/dt . The proposed approach for designing that balancing netw ork results in a small value of capacitance as well as a small value of discharging current which makes the dynamic balancing network more efficient and compact. The influence of dynamic balancing resistance and cro wbar current limiting inductance on v oltage imbalance, charging current and discharging current is explained. This method also allows one to operate a series connected string of thyristors without any complex pulse synchronizing circuit that is normally found in cro wbar applications. The analysis done for the balancing network includes 17 component tolerance to capture the worst case circuit operating conditions. F or the experimental v alidation two practically encountered delays, the dif ference in propagation delay among gate signals of thyristors and difference in turn-on delay among thyristors, are considered. Experimental results on a 12 k V , 1 k A crowbar shows excellent results and confirms the theoretical analysis and the proposed design procedure. 9. Ackno wledgment The work is supported by Ministry of Electronics and Information T echnology , Go vt. of India, through NaMPET programme and Department of Atomic Ener gy (D AE), Go vernment of India through Institute for Plasma Research, Gandhinagar , India. The authors thank Mr . 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