Analysis, Dimensioning and Robust Control of Shunt Active Filter for Harmonic Currents Compensation in Electrical Mains

Analysis, Dimensioning and Rob ust Contr ol of Shunt Active Filter f or Harmonic Currents Compensation in Electrical Mains Andrea T illi, Lorenzo Marconi, Christian Conficoni Center for Complex A utomated Systems (CASY), Dept. of Electr onics, Computer Engineering and Systems (DEIS), University of Bologna, V iale Risor gimento 2, 40136 Bologna Italy Abstract In this chapter some results related to Shunt Activ e Filters (SAFs) and obtained by the authors and some coauthors are r eported. SAFs are complex power electronics equipments adopted to compensate for cur- rent harmonic pollution in electric mains, due to nonlinear loads. By using a proper "floating" capacitor as energy reservoir , the SAF purpose is to inject in the line grid currents canceling the polluting har- monics. Control algorithms play a ke y role for such devices and, in general, in many po wer electronics applications. Moreov er , systems theory is crucial, since it is the mathematical tool that enables a deep understanding of the in volv ed dynamics of such systems, allowing a correct dimensioning, beside an effecti ve control. As a matter of facts, current injection objectiv e can be straightforwardly formulated as an output tracking control problem. In this fashion, the structural and insidious marginally-stable internal/zero dynamics of SAFs can be immediately highlighted and characterized in terms of sizing and control issues. For what concerns the control design strictly , time-scale separation among output and internal dynamics can be effecti vely exploited to split the control design in different stages that can be later aggregated, by using singular perturbation analysis. In addition, for robust asymptotic output tracking the Internal Model Principle is adopted. In authors’ opinion, SAF case is an illustrativ e example of common issues in dimensioning and control of complex power electronics equipments, hence the proposed design approach can be generalized for such class of systems (e.g. large-po wer electric driv es; generators and con verters, particularly for re- new able energies; Uninterruptible Po wer Supplies, UPS, and power supplies for special applications as particle accelerators). Remarkable the role of "system theory approach" in enlightening crucial sizing issues, this f act strongly testifies how relev ant the "control vie wpoint" is in all the fields of engineering, particularly when complex dynamic beha vior is requested. The presented chapter has been in vited for possible publication (after a re view process) in the book "Robust Control / Book 1", ISBN 978-953-307-421-4, by INTECH (www .intechweb .org). 1. Introduction Harmonic pollution in the A C mains determines additional power losses and may cause malfunction- ing or even damage to connected equipments. Distortion of the currents circulating on electric mains is mainly originated by non linear loads, as A C/DC uncontrolled rectifiers used for motor drives, that absorb undesired current harmonics. Therefore, local countermeasures hav e to be taken in order to keep the portion of grid af fected by distortion as small as possible, hence preventing relev ant power losses and “saving” other equipments, connected to the rest of the grid. T raditionally , passiv e filtering components hav e been adopted to cope with harmonic compensations, howe ver they are affected by se veral drawbacks; they are very sensitive to network impedance varia- tion and environmental conditions, moreover they need to be tuned on fixed frequencies. In order to ov ercome those limitations, in the last decades, thanks also to the fast growth in power electronics and control processor technologies, a remarkable research attempt has been devoted to the study of the so- called Activ e Po wer Filters (APFs), both from a theoretical and technological point of vie w (see Gyugyi & Strycula (1976), Akagi (1996), Singh & Al-Haddad (1999)). These de vices are able to properly work in a wide range of operating conditions, providing better performance and overtaking intrinsic limita- tions of passive devices, they are far more insensitive to network impedance, they can be tuned onto different frequencies just varying some software parameters. Furthermore, the system reliability is im- prov ed, resonance phenomena are av oided and a diagnosis system can be implemented on the control processor to monitor the system v ariables and adopt some recov ery strategy in case of faulty conditions. In this chapter , the general issues related to analysis, dimensioning and control of a particular class of APFs, the so-called Shunt Acti ve Filters (SAFs), are addressed; the main purpose of this kind of power system is to inject into mains a proper current, in order to cancel out, partially or totally , the power distortions generated by nonlinear loads. The SAFs considered in this work are based on a three-phases three-wires A C/DC boost conv erter topology (see Fig. 1) connected in parallel to the distorting loads. The first step to properly design a SAF is the selection of suitable hardware components; as it will become clear in the next section, owing to the structural properties of the system, the sizing procedure cannot be considered apart from the canonical control aspects, hence a correct dimensioning algorithm (Ronchi & Tilli, 2002) is proposed to ensure feasibility of the desired control objectiv es and to minimize costs. In addition, according to such method, it is shown ho w a time-scale separation between dif ferent dynamics of SAF usually takes place “for free”. This point is v ery useful for control design and stability analysis. Once a correct hardware sizing has been carried out, the first control issues to deal with are: the cur- rent/power control algorithm and the load current analysis method adopted to define the filter current reference. V arious solutions have been proposed in literature. As regards current/po wer harmonic tracking, in (Chandra et al., 2000) an hysteresis current control (Kazmierko wski & Malesani, 1998) is proposed, while in (Jeong & W oo, 1997) predictiv e current control is adopted. F or what concerns the generation of the filter currents reference, beside F ast Fourier T ransform T echniques, instantaneous power theory (Akagi et al., 1984), time domain correlation techniques (V an Harmelen & Enselin, 1993), notch filter theory (Rastogi et al., 1995) and other methods hav e been proposed. Solution based on state observer ha ve been proposed, too, as in (Bhattacharya et al., 1995) and (Tilli et al., 2002). Howe ver , what renders the SAF control problem challenging and different from other con ventional tracking problems is the presence of peculiar and unstable internal dynamics, given by the voltage dy- namics of the DC-link capacitor bank. This capacitor bank is the main energy storage element, which provides the voltage, modulated by the control, to steer the filter currents and, at the same time, is re- quired to oscillate to exchange energy with the line and the load to compensate for current harmonics. Actually , this element needs to be carefully considered also in the previously-mentioned dimensioning stage; a correct capacitor sizing is crucial for control objective feasibility , whatev er control technique is adopted. Moreover , it can be shown that, if perfect harmonic compensation is achiev ed, the DC-link voltage dynamics are unstable, due to the system parasitic resistances that lead to a slow discharge of the capacitor . Hence, a suitable stabilizing action for DC-link voltage dynamics needs to be provided. Since no additional circuit is used to feed the DC-link capacitor independently of the three-phase port used to inject currents, (see Fig. 1), the voltage stabilization would need to be integrated with the con- Fig. 1. Shunt Acti ve Filter scheme. troller devoted to harmonic compensation (the AC/DC boost-based SAF is an underactuated system). This is a crucial point and it has to be tackled preserving harmonic compensation performances as far as possible. In this work a power/current controller, based on Internal Model Principle, (see Marconi et al. (2003), Marconi et al. (2004), Marconi et al. (2007)) is designed in order to cancel current harmonics, ensuring robustness with respect to SAF parameter uncertainties. By exploiting the internal model approach, the proposed solution also allows to merge and solve at the same time the two above-mentioned problems of current harmonics isolation and current reference tracking. As regards the rob ust stabilization of the DC-link v oltage internal dynamics, a cascade control structure is proposed. An additional volt- age controller , acting on the references of the power/current controller, is introduced. This controller is designed taking into account the structural voltage oscillations required for harmonic compensation and minimizing the impact on harmonic compensation. In particular, by exploiting a proper av eraging (Sanders et al., 1991) of the capacitor voltage dynamics, the average value of the capacitor voltage is chosen as output variable to be controlled (Hanschk e et al., 2006). As far as the ov erall stability is concerned, the previously mentioned time-scale separation between portions of SAF dynamics can be effecti vely exploited to decouple power/current tracking and voltage stabilization control problems, using averaging and singular perturbation theory techniques (Khalil, 1996). This chapter is organized as follows. In Section 2, the general framework is described, the SAF model is deri ved and the control objecti ves are formally defined. In Section 3, two methodological approaches are presented for the SAF components sizing. The first one is based on the knowledge of the load cur- rents harmonic spectrum, the values selected for the hardware components are the minimums allowing the SAF to deal with the considered load distortion. Differently , the second approach is related to the maximum current of the AC/DC boost switching devices. In this case the selected components values are the minimums which enable the SAF to compensate for all possible loads giving distorted currents smaller or equal to the switches peak v alue. In Section 4 both the internal model-based po wer/current controller and the av eraging voltage controller design are presented, stability analysis is carried out re- lying upon the time-scale separation imposed by the design algorithm; both the power and the voltage subsystem are proven to be asymptotically stable, then practical stability of the overall system is claimed exploiting general results on two time-scale averaged systems (T eel et al., 2003). The effecti veness of the proposed control solution is tested in Section 5 through simulations. 2. Shunt active filter model and control pr oblem statement The scheme of the shunt active filter considered in this chapter is reported in Fig. 1, as mentioned in the introduction it is based on a three-phase three-wire AC/DC boost con verter , where the main energy storage element is a DC-bus capacitor , while the inductances are exploited to steer the filter currents by means of the con verter voltages. The switching de vices of the three-leg bridge (also called "‘in verter"’) are usually realized by IGBTs (Insulated Gate Bipolar T ransistors) and free-wheeling diodes. In this work the following notation is used to denote the SAF variables; v mabc = ( v ma , v mb , v mc ) T is the mains voltage sinusoidal balanced and equilibrated tern, i m = ( i ma , i mb , i mc ) T are the mains currents, i l = ( i l a , i l b , i l c ) T are the load currents, while i = ( i a , i b , i c ) T are the filter currents. L indicates the v alue of the inductances, and C the DC-link bus capacitor value. 2.1 Mathematical model Considering the inductors dynamics, the filter model can be expressed as   v ma ( t ) v mb ( t ) v mc ( t )   − L d dt   i a ( t ) i b ( t ) i c ( t )   − R   i a ( t ) i b ( t ) i c ( t )   =   u x ( t ) u y ( t ) u z ( t )   v ( t ) − v N K   1 1 1   (1) where R is the parasitic resistance related to the inductance L and to the cables, v N K is the voltage between the nodes N and K reported in Fig. 1, v ( t ) is the voltage on the DC-link capacitor , and u 1 = ( u x , u y , u z ) T is the switch command vector for the legs of the conv erter . Since a PWM (Pulse W idth Modulation) strategy is assumed to control the in verter , the above-mentioned control inputs can be considered such that u 1 i ∈ [ 0, 1 ] , i = x , y , z . According to the three-wire topology for any generic voltage/current v ector x it holds ∑ i = a , b , c x i = 0 (2) hence, from the sum of the scalar equations in (1) it follows that v N K = u x ( t ) + u y ( t ) + u z ( t ) 3 v ( t ) (3) defining u abc = [ u a ( t ) , u b ( t ) , u c ( t ) ] T =   u x ( t ) u y ( t ) u z ( t )   − u x ( t ) + u y ( t ) + u z ( t ) 3   1 1 1   (4) it can be verified by direct computations that [ 1 1 1 ] u abc ( t ) = 0 ∀ t ≥ 0. (5) For what concerns the state equation relative to the capacitor voltage dynamics, it can be derived con- sidering an ideal inv erter and applying a po wer balance condition between the input and the output of the filter , then replacing (3) into (1), the complete filter model results d i dt = − R L I 3 i ( t ) − v ( t ) L u abc ( t ) + 1 L v mabc d v dt = 1 C u T abc ( t ) i ( t ) (6) where the filter currents dynamics have been written in a more compact form with respect to (1), mul- tiplying the current vector by the identity matrix of suitable dimension I 3 . Exploiting equations (3), (5), the system model can be reduced to the standard two-phase planar repr esentation of a three-phase balanced systems (Krause et al., 1995), which can be obtained applying the following coordinates trans- formation i α β ( t ) = [ i α i β ] T = α β T abc i ( t ) u α β ( t ) = [ u α u β ] T = α β T abc u abc ( t ) v m α β = [ v m α v m β ] T = α β T abc v m α β T abc = 2 3 " 1 − 1 2 − 1 2 0 √ 3 2 − √ 3 2 # (7) the SAF dynamics expressed in this α − β reference frame become d i α β dt = − R L I 2 i α β ( t ) − v ( t ) L u α β ( t ) + 1 L v m α β d v dt = 3 2 C u T α β ( t ) i α β ( t ) (8) according to the hypothesis of three-phase balanced sinusoidal line, the ideal main voltage tern can be expressed in the abo ve-defined bi-dimensional reference frame as follo ws [ v m α v m β ] T = V m [ cos ( ω m ) sin ( ω m )] T where V m is the voltage amplitude and ω m the grid angular frequency . F or what concerns the control vector u abc , in this reference frame the eight possible configurations of the switching network (reported in T ab . 1) can be mapped in the α − β plane, obtaining the vertex es and the origin of the feasibility space illustrated in Fig.2, while each point in the hexagon can be obtained as mean value in a PWM period. As it will become clear in the next sections, in order to simplify the control objecti ves definition and the controller design, it is very useful to adopt a further transformation from the two-phase current variables [ i α i β ] T to a two-phase real-virtual (imaginary) po wer variables defined as x = [ x d x q ] T = d q T α β i α β (9) where d q T α β = V m  cos ( ω m t ) sin ( ω m t ) − sin ( ω m t ) cos ( ω m t )  . In this so-called synchr onous coordinate setting, aligned with the mains voltage vector , the model of the SAF is expressed as ˙ x = M ( R , L ) x − v L u d q + d 0 ˙ v = ε 2 u T d q x (10) u x u y u z u a u b u c u α u β 0 0 0 0 0 0 0 0 1 0 0 2/3 -1/3 -1/3 2/3 0 1 1 0 1/3 1/3 -2/3 1/3 1/ √ 3 0 1 0 -1/3 2/3 -1/3 -1/3 1/ √ 3 0 1 1 -2/3 1/3 1/3 -2/3 0 0 0 1 -1/3 -1/3 2/3 -1/3 -1/ √ 3 1 0 1 1/3 -2/3 1/3 1/3 -1/ √ 3 1 1 1 0 0 0 0 0 T able 1. Control function table. −0.8 −0.4 0 0.4 0.8 −0.8 −0.4 0 0.4 0.8 b c a Fig. 2. Hexagon of feasible u abc . where d 0 =  E md / L 0  , M ( R , L ) =  − R / L ω m − ω m − R / L  , ε = 3 CE md , E md = V 2 m , u d q = d q T α β u α β (11) it is further to notice that, since the filter currents, the mains voltage and the DC-link voltage are mea- surable, the full state ( x , v ) is av ailable for feedback, moreov er the actual control action u = [ u x u y u z ] can be determined from u abc , which in turn can be deriv ed from u d q . As regards the load description, the same two-phase real-virtual power representation can be used, in particular following (Akagi et al., 1984), the load currents can be approximated as periodic signals giv en by the sum of a finite number N of harmonics, with frequencies multiple of f m = ω m / 2 π . Hence the load currents can be expressed in po wer variables as x l j = X l j 0 + N + 1 ∑ n = 1 X l jn cos ( n ω m t + ψ jn ) , j = d , q (12) where the harmonics amplitudes X l d 0 , X l q 0 , X l d n , X l qn and phases ψ d n , ψ qn are constants. Since the load currents and the mains voltages are measurable, also the variables ( x l d , x l q ) will be considered known and av ailable for control purpose. 2.2 Problem statement and contr ol objectives Roughly speaking the main control objective of the considered SAF is to steer the v ariables x d , x q , injecting power into the line to compensate for the load harmonics. Ho wever the ability of tracking current references relies upon the energy stored in the DC-link capacitor , which is the main power source of the filter , therefore another general objectiv e is to keep the DC-link voltage confined in a suitable region, to avoid ov ercharge and, at the same time, to ensure the capability to steer the filter currents. On the other hand the ability of maintaining DC-link voltage into a suitable region is strictly related to the po wer exchanged with the mains, which in turn is affected by the current harmonics to be compensated for . The general control objectiv e is then two-folds; one related to the tracking of current disturbances, the other concerns the voltage internal dynamics stabilization. In this paragraph a precise and feasible control problem is formally defined, recalling the considerations made above, and assuming that a suitable dimensioning, that will be deeply discussed in the next section, has been carried out. Bearing in mind the power v ariables representation of a generic nonlinear load expressed in (12), it turns out that the only desired load component is X l d 0 , since it represents first-order harmonics aligned with the mains voltages, while the remaining part of the real component x l d − X l d 0 is an oscillatory signal with null balance over a line period, and the imaginary component x l q represent a measure of the misalignment between mains ideal voltage and load currents (see Mohan et al. (1989)) and do not contribute to the power flo w . In this respect, the terms x l d − X l d 0 , x l q are undesired components which should be canceled by the injected filter currents, hence ideally the control problem can be formulated as a state tracking problem, for system (10), of the following reference x ∗ ( t ) = [ x ∗ d x ∗ q ] T =  X l d 0 − x l d − x l q  T (13) a prefect tracking of this reference would ensure pure sinusoidal mains currents perfectly aligned with the mains voltages. Howe ver , this ideal objective is in contrast with the requirement to have a DC-link voltage bounded behavior . In order to formally motiv ate this claim, consider the steady state voltage dynamics in case perfect tracking of the power reference x ∗ ( t ) is achieved, after some computations it results d v 2 dt = ε L ( d 0 + M ( R , L ) x ∗ ( t ) − ˙ x ∗ ( t ) ) T x ∗ : = ε Ψ ( x ∗ ( t ) ) (14) the signal ε Ψ ( x ∗ ( t ) ) which drives the integrator is periodic with period T = 1 / f m , and it is composed by the sum of a zero mean value signal ε L ( d 0 − ˙ x ∗ ) T x ∗ , and the signal ε L ( M ( R , L ) x ∗ ) T x ∗ which has negati ve mean value as long as parasitic resistance R or reference x ∗ are not zero. By this, no matter the starting voltage value of the DC-link, the capacitor will be discharged and the voltage will drop, providing a loss of controllability of the system. T o avoid this phenomenon, the reference must be revised, taking into account an additional po wer term, which should be drained from the line grid by the active filter, in order to compensate for its power losses. Follo wing this motiv ation, and recalling that the unique useful component for the energy exchange is the real part of the po wer variables, the ideal reference signal (13) is modified as x ∗ ϕ 0 = x ∗ + ( ϕ 0 0 ) T (15) in which ϕ 0 is a solution of the following equation R ϕ 2 0 − E md ϕ 0 + R f m Z 1 / f m 0 ( x ∗ 2 d ( τ ) + x ∗ 2 q ( τ ) ) d τ = 0 (16) this represents the power balancing condition which guarantees that the internal voltage dynamics in case of perfect tracking of the modified reference x ∗ ϕ 0 is d v 2 ( t ) dt = ε Ψ ( x ∗ ϕ 0 ( t ) ) (17) and the right hand side ε Ψ ( x ∗ ϕ 0 ) is periodic with period 1 / f m with zero mean v alue. A brief discussion is needed for the solutions of equation (16), it has two real positiv e solutions if the following condition is verified E 2 md ≥ 4 R 2 f m Z 1 / f m 0 ( x ∗ 2 d ( τ ) + x ∗ 2 q ( τ ) ) d τ (18) from a physical viewpoint relation (18) set an upper bound on the admissible undesired components which can be compensated and on the parasitic resistance R , howe ver , as typically E md >> R , this condition is not limitativ e at all. The two solutions of (16) under condition (18) are ϕ 0 ≈ R E md f m Z 1 / f m 0 ( x ∗ 2 d ( τ ) + x ∗ 2 q ( τ ) ) d τ ≈ 0 ϕ 0 ≈ E md R (19) the first solution, minimizing the po wer drained from the line grid to compensate the power losses, is the physically most plausible, because the power consumed by parasitic resistances in the filter is usually quite small, hence it will be considered throughout the chapter . The control problem which will be faced in this work can now be precisely stated; the issue is to design the control vector u abc in a way such that the follo wing objectives are fulfilled: A ) Giv en the reference signal x ∗ ϕ 0 defined in (15), asymptotic tracking must be achiev ed, that is lim t → ∞ ( x ( t ) − x ∗ ϕ 0 ) = 0; (20) B ) Gi ven a safe voltage range [ v m , v M ] , with v M > v m > 0, and assuming v ( t 0 ) ∈ [ v m , v M ] , it is required that v ( t ) ∈ [ v m , v M ] , ∀ t > t 0 ; (21) it can be verified that the tracking of the modified po wer reference is potentially achiev able keeping the voltage dynamics inside the safe region, only if the zero mean v alue oscillating component of ε Ψ ( x ∗ ϕ 0 ) is properly bounded, this can be ensured by a suitable capacitor design. In the regulator design, saturation of the actual input u 1 , imposed by PWM strategy , will not be taken explicitly into account, also this approximation takes advantage of a correct sizing methodology; as it will become clear in Section 3, a suitable choice of the DC-link voltage lower bound v m , depending on the currents to be compensated for , has to be made to meet the constraint u 1 ∈ [ 0, 1 ] , at least when the power tracking error is reasonably small. A further consideration needs to be made on the requirement v ( t 0 ) ∈ [ v m , v M ] ; according to the A C/DC boost con verter theory (Mohan et al., 1989), the natural response of the system would lead the DC-link voltage at twice the line voltage peak value, due to the resonant behavior of the L C pair and the free- wheeling diodes of the switching bridge. If a proper design has been performed, this value is expected to be greater than the voltage range lower bound v m ; hence, after a transient period, the controller can be switched on having the initial v oltage value inside the admissible region as required by objecti ve B . Finally it is further to remark that x ∗ ϕ 0 depends on parasitic resistance R through (16), hence it has to be considered as an unknown variable, to be reconstructed by estimating the power losses by means of a proper elaboration of the DC-link voltage signal. 3. Shunt active filter sizing methodology The aim of this section is to present a precise algorithm to properly select the SAF hardware compo- nents, tw o different design objectiv es are considered, the first is to select the minimal component v alues dependent on the lev el of current distortion imposed by the load, while the second is to find the min- imum capacitor v alue necessary to compensate all the possible loads compatible with the maximum current rating of the in verter switching devices. Both the methods are control-oriented, that is they en- sure the feasibility of control objectives stated in 2.2 and that control input saturation is av oided under nominal load and line voltage conditions. The proposed design method is based on the model derived in Section 2, a further approximation is con- sidered with respect to equation (6); the inductors are modeled as pure inductance, that is the parasitic resistance R is neglected, while ideal mains voltage tern and con verter switches are considered as in the previous section. 3.1 Inductance value selection The inductance value can be selected regardless the loads, hence this part of the design procedure is the same for both the design objectiv es previously defined. The design criterion is based on the maximum current ripple ∆ I M p p allowed for the filter currents; current ripple is a consequence of the PWM technique applied to obtain the reference command value u ∗ abc , it has to be bounded in order to limit high frequency distortion. The actual command vector u abc ( t ) and filter current i ( t ) are affected by a ripple component i ( t ) = i ∗ ( t ) + ∆ i ( t ) u abc ( t ) = u ∗ abc ( t ) + ∆ u abc ( t ) (22) substituting these expressions in the state equation (6) it turns out L ∆ i ( t ) dt = − ∆ u abc ( t ) v ( t ) (23) by simple computation it can be showed that the worst ripple case occurs when the desired command value u ∗ abc is in the middle of a feasibility hexagon side (see Fig. 3). In this condition, assuming that the DC-link voltage has constant v alue V in a PWM period, the peak to peak current ripple is ∆ I p p = Z t + T s / 2 t d ∆ i ( t ) dt dt = V 6 f P W M L (24) where the sampling period T s and the PWM frequency f P W M are assumed already set before starting the sizing procedure. If the peak to peak ripple must be bounded by the desired maximum v alue ∆ I M p p , the following inequality needs to be fulfilled L ≥ v M 6 f P W M ∆ I M p p ⇒ L min = v M 6 f P W M ∆ I M p p (25) the upper bound of the voltage range v M depends only on the kind of capacitor and it can be sup- posed already chosen before starting the design procedure, hence the minimum inductance value L min compatible with the desired maximum current ripple can be selected applying equation (25). 0 0.2 0.4 0.6 0 0.2 0.4 0.6 p3 p2 p1 Fig. 3. Current ripple worst case. −200 −100 0 100 200 −200 −100 0 100 200 Fig. 4. Hexagon of feasible filter current. 3.2 Load-based approach Let us now consider the first design algorithm based on the knowledge of the load to be compensated for . The load distortion will be modeled as in equation (12), taking into account the constraint on the maximum current I max of the device implementing the bridge switches. The switching de vices sizing depends on the total amount of power (distorted and reactiv e) P = 3 V mRM S I SAF RMS that the filter has to compensate for (if the load is known then P is known), hence by the route mean square value I SAF RMS , the maximum current that the switches need to drain can be readily obtained as I max = √ 2 I SAF RMS . The desired filter currents (denoted with ∗ ) necessary to fulfill the tracking objecti ve A defined in 2.2 can be ef fectively imposed by the con verter if each component is less than the maximum allowed v alue, i.e i ∗ ( t ) = [ i ∗ a ( t ) i ∗ b ( t ) i ∗ c ( t ) ] T ≤ I max [ 1 1 1 ] T , ∀ t (26) this feasibility condition can be graphically represented considering that each projection of the filter currents vector must be less then I max , hence the feasibility space is an hexagon similar to that reported in Fig. 4 (obtained taking P = 45 k V AR as filter size, V mRM S = 220 V and then I max = 70 A ). Therefore condition (26) can be readily checked considering the inscribed circle in the feasibility hexagon. If the load currents do not satisfy constraint (26) the number of current harmonics to be compensated for has to be reduced, differently , when the filter performance cannot be decreased, the opportunity to connect two shunt acti ve filters to the same load can be considered. Assuming that an inductance value such that L ≥ L min has been selected, the v oltages at the input of the six switches bridge can be calculated as v ∗ d q ( t ) = v ( t ) u ∗ d q ( t ) =  V m 0  − L d i ∗ d q dt +  0 ω m − ω m 0  i ∗ d q (27) the abov e equation is obtained by in version of equation (10) with R = 0 and expressing the model in the synchr onous reference frame in current rather than in power variables, in order to directly consider the load currents in the design approach. The constraints on the command inputs need to be considered too, by (27) the inductance value must be as lo w as possible in order to mak e u ∗ d q feasible, taking into account also the current ripple limitation we select L = L min . As mentioned, the choice of the of the capacitor voltage lower bound value plays a key role to avoid saturation issues on command inputs, this can be easily verified approximating the hexagon in Fig. 2 with the inscribed circle. In order to av oid control action saturation (assuming perfect power tracking) it must be imposed that || u ∗ abc || = || v ∗ abc ( t ) || v ( t ) ≤ || v ∗ abc ( t ) || v m ≤ r in = 1 √ 3 , ∀ t (28) with r in the radius of the inscribed circle and v ∗ abc = v ( t ) u ∗ abc . From (28) design equation for v m can be obtained v M ≥ v m ≥ || v ∗ abc ( t ) || r in , ∀ t ∈  n f m , n + 1 f m  , n = 0, 1, . . . (29) usually v m is o versized with respect the value gi ven by the inequality abov e, in order to a void saturation ev en if non-zero tracking errors are present. If condition (29) cannot be satisfied, some alternatives need to be considered; the capacitor can be changed in order to adopt an higher upper bound v M , when the costs of the project have to be limited and the kind of capacitor cannot be substituted, the number of harmonics considered must be reduced until (29) is satisfied. T o preserve the number of harmonics to compensate, the inductance value can be reduced, penalizing the current ripple and then tolerating a greater high frequency distortion. The capacitor value can then be selected assuming an ideal conv erter and writing the balance equation between the instantaneous reference power at the input of the six switches bridge and the power of the DC-link capacitor , hence p f il t ( t ) = [ v d q ( t ) ] T i ∗ d q ( t ) = d dt  1 2 Cv 2 ( t )  (30) the corresponding energy can be calculated as E f il t ( t ) = Z t t 0 p f il t ( τ ) d τ (31) by the hypothesis of sinusoidal load currents and ideal mains voltages E f il t ( t ) is periodic of frequency f m and its mean value is zero. Defining E max = max | E f il t ( t ) | v re f = v M + v m 2 (32) and imposing that the voltage variation corresponding to E max is v re f − v m , the capacitor value design equation can be written as C = 2 E max v 2 re f − v 2 m (33) 3.3 Switches-based approach As stated at the beginning of this section, a dif ferent design method aims to find the capacitor value that makes the filter able to compensate for the worst load compatible with the switches maximum current. If the resulting capacitor value is not too expensi ve, this method allo ws to design the filter only knowing the amount of current that has to be compensated. During the optimization procedure the load currents need to be the only varying parameters while all the other values must be fixed. The inductance value is chosen equal to the minimum compatible with the allowed ripple, while the minimum capacitor voltage v m is supposed sufficiently low to make simple the voltage control, and, at the same time, the resulting capacitor value feasible. Writing the filter currents spectrum in the d − q synchronous reference frame, an expression similar to (12) can be obtained i j ( t ) = I j 0 + N + 1 ∑ n = 1 I jn cos ( 2 π n f m t + ψ jn ) , j = d , q (34) the parameters to be varied in order to calculate the worst E max are the ( 2 N + 1 ) + 1 magnitudes and the 2 N + 1 phases, so the following optimization problem E worst max = max z max t | Z t t 0 [ v d q ( τ ) ] T i d q ( τ ) d τ | (35) has to be solv ed with respect to the array z of 4 ( N + 1 ) + 1 variables, taking into account the following constraints • switches currents must be less than the maximum allowed, that is the current vector must be inside an hexagon similar to that reported in Fig. 4. This can be easily checked approximating the hexagon with its inscribed circle; • the control output must be feasible, that is the vector u abc must be inside the hexagon reported in Fig. 2. This can be easily checked approximating the he xagon with its inscribed circle; • harmonics components phases ha ve to be greater than − π and less than π . Once E worst max has been determined, substituting its value in (33), the capacitor v alue relati ve to the switches-based design approach can be selected. In the discussion above, ideal mains v oltages have been assumed, if also the grid line voltages are distorted, the capacitor has to provide more energy to the load, hence its value must be higher than the one calculated under ideal conditions. In case of ideal mains voltages the load instant power is the one calculated in (12) and the only power term that the filter must deli ver is x l d n = ∑ N + 1 n = 1 X l d n cos ( n ω m t + ψ d n ) = V m i l d n having zero mean value. If the mains voltages are distorted, their representation in the synchronous reference frame is v md q ( t ) = [ V m + v md n , v mq ] T (36) line v oltages harmonic perturbation produces additiv e terms in the load instantaneous po wer expression, that by direct computation can be written as p l ad d = v md n ( t ) i l d n ( t ) + v mq i l q ( t ) (37) the above equation shows that the filter has to provide more power to the load, furthermore the po wer mean value in a PWM period can be different from zero. Hence also assuming that the mean value becomes zero in a finite time, the capacitor must be oversized with respect to the ideal situation, in order to accumulate more energy . Fig. 5. Controller structure. 4. Robust contr oller design In this section the control problem defined in 2.2 is addressed, relying upon a suitable capacitor value giv en by the procedure described in the previous section, the two interlaced objectives A and B defined in 2.2 can be approached individually by exploiting the principle of singular perturbation. T wo inde- pendent controllers (reported in the block diagram of Fig. 5) will be designed. An internal model-based controller (IMC) is proposed in order to deal with the problem of robust reference tracking (defined in objectiv e A ) for the fast subsystems composed by the power variables dynamics, while an independent voltage controller for the slow DC-link voltage subsystem is designed to produce a reference modifi- cation η which compensate the unknown power losses term ϕ 0 , allo wing to achieve objectiv e B . The av eraged v oltage value is chosen as the controlled v ariable, and a phasor v ariables representation is exploited to design the regulator , this choice allows for the necessary voltage oscillation during nom- inal operation, and improves the voltage dynamics behavior with respect to other proposed solutions (Marconi et al., 2007). Stability analysis is carried out in two steps; the reduced averaged dynamics , obtained replacing the steady state of the fast subsystem into the slow voltage dynamics and carrying out the av erage value to obtain a phasor variables representation, and the boundary layer system , ob- tained considering the SAF currents dynamics and an ideal energy storage element, are proved to be asymptotically stabilized by the proposed controllers. Then practical stability for the overall closed- loop error system is stated exploiting well-established singular perturbation and two time-scale systems theory results. Before detailing the proposed control structure, consider the first preliminary control law ¯ u ( t ) = v ( t ) u d q ( t ) (38) which is alw ays well defined provided that v ( t ) ≥ v m > 0 for all t ≥ 0 according to objecti ve B . Replac- ing (38) into (10) yields ˙ x = M ( R , L ) x + 1 L ¯ u + d 0 d v 2 dt = ε ¯ u T x (39) now consider the modified po wer reference x ∗ η = x ∗ + ( η 0 ) T (40) and define the change of variables ˜ x = x − x ∗ η , ˜ z = v 2 − V ∗ 2 (41) where V ∗ 2 = ( v 2 m + v 2 M ) / ( 2 ) is the reference value for the square DC-link voltage. Note that the requirement B of having v ( t ) ∈ [ v m v M ] for all t ≥ t 0 can be equiv alently formulated in the error variable ˜ z requiring ˜ z ( t ) ∈ [ − l ∗ l ∗ ] for all t ≥ t 0 , with l ∗ = ( v 2 M − v 2 m ) / 2. The complete system (39) can be then expressed in the error v ariables defined in (41), the transformed model results ˙ ˜ x = M ( R , L ) ˜ x − 1 L ¯ u + d 0 − ˙ x ∗ η + M x ∗ η ˙ ˜ z = ε ¯ u T [ ˜ x + x ∗ η ] . (42) The controller design will be carried out considering the error dynamics in (42), in summary the idea is to steer the closed loop dynamics toward a steady state in which ˜ z is free to oscillate within the admissible re gion, b ut its mean v alue is steered to zero (i.e the DC-link v oltage mean v alue is steered to V ∗ ), and ˜ x is steered to zero, i.e the power x follows a reference which is the sum of the term x ∗ , which takes into account the undesired harmonic load components, and a constant bias η which is needed in order to compensate the power losses and to make the range [ v m v M ] an in variant subspace for the voltage dynamics. 4.1 Avera ging v oltage controller In order to fulfill objective B the voltage dynamics need to be stabilized, in this respect the subsystem composed by the capacitor voltage dynamics will be considered, a suitable reduced avera ged system will be sought, and then a controller for the capacitor voltage DC component will be designed. The first step is to av erage the voltage dif ferential equation to obtain the dynamics in the so-called phasor-variables , then, a control law , itself expressed on phasor representation, can be designed fol- lowing an approach similar to that proposed in (V alderrama et. al, 2001), ho wever in this w ork the only voltage subsystem is controlled using phasor variables, while the power subsystem is controlled in the real time domain. The controlled variable is chosen to be the time-windo w av eraged v alue ˜ z a of the square voltage error ˜ z , and the averaging is performed o ver the time interval [ t − T , t ] . In terms of (Sanders et al., 1991) this av erage value is a zero-order phasor defined as ˜ z a ( t ) = Z t t − T ˜ z ( τ ) d τ (43) the fact that ˜ z a is a zero-order phasor allows to obtain its deriv ative by simply applying the same av er- aging procedure to its differential equation in (42) ˙ ˜ z a = 1 T Z t t − T ˜ z ( τ ) d τ = ε Z t t − T ¯ u T [ ˜ x + x ∗ η ] d τ (44) note that the average voltage deriv ative can also be expressed as the difference over one period of the actual voltage, hence d dt ( ˜ z a ) = d dt Z t t − T ˜ z ( τ ) d τ = ˜ z ( t ) − ˜ z ( t − T ) T (45) this insight connotes the availability of ˜ z a for measurement in real time, and, as it will later clarified, it is of crucial importance for an actual implementation of the controller . All further elaborations will focus on the integral-dif ferential equation (44) representing the av eraged error voltage dynamics. This equation depends on ¯ u which is actually provided by the power tracking controller , to eliminate ¯ u consider that the differential equation for ˜ x in (42) can be rewritten as ¯ u = L ( M ( R , L ) x ∗ η − ˙ x ∗ η + M ( R , L ) ˜ x + d 0 − ˙ ˜ x ) (46) replacing (46) into (44) the following equation is obtained ˙ ˜ z a = ε L T Z t t − T ( M ( R , L ) x ∗ η − ˙ x ∗ η + d 0 ) T x ∗ η d τ + ε L ˜ D ( ˜ x ) (47) where ˜ D ( ˜ x ) collects all the terms depending on the power tracking error ˜ x . The next step is to exploit the fact that the reference term x ∗ is T -periodic ( T = 1 / f m ), hence it results in a constant value when av eraged over this period, this is a key advantage of the a veraging approach for the v oltage system. The T -periodic terms in (47) can be summarized to D ∗ = 1 T Z t t − T [( M ( R , L ) x ∗ − ˙ x ∗ + d 0 ) T x ∗ ] d τ (48) since x ∗ is periodic in T , D ∗ is a constant disturbance, and, due to power losses induced by the parasitic resistance R , it also follows that D ∗ < 0. For further simplification the integral operator can be applied to the occurring deriv ative terms. Using definitions (11), (40), after some computations the averaged error voltage dynamics can be e xpressed completely in phasor variables ˙ ˜ z a = ε [ E md η a − 2 R ν a − L ˙ ν a + LD ∗ + L ˜ D ] (49) where the following nonlinear term has been defined ν ( t ) = η ( t )  1 2 η ( t ) + x ∗ d  (50) which enters (49) with its av erage and its averaged deri vativ e ν a ( t ) = 1 T Z t t − T ν ( τ ) d τ ˙ ν a ( t ) = ν a ( t ) − ν a ( t − T ) T (51) the av eraged error voltage system is thus controlled by means of the av eraged control input η a ( t ) = 1 T Z t t − T η ( τ ) d τ . (52) According to singular perturbation theory , the voltage controller design can be carried out considering only the r educed dynamics , obtained confusing the value of ˜ x with its steady state value ˜ x = 0. As previously remarked, this approximation can be introduced thanks to the small value of ε which, multiplying the v oltage dynamics in the second of (42), makes the v oltage subsystem much slower with respect to the power dynamics in the first of (42) (this phenomenon is usually referred as two time-scale system beha vior) that will approach the steady state much faster then ˜ z . Thus reduced voltage dynamics can be obtained by (49) simply dropping the coupling term ˜ D , because by definition ˜ D ( 0 ) = 0. The nonlinear terms ν a , and ˙ ν a cannot be managed easily , beside non-linearity they contain an inte gral, a time delay and a time-varying term x ∗ d . In order to simplify the mathematical treatment, a sort of linearized version of system (49) will be considered. This linear approximation is motivated by se veral facts; since the parasitic resistance R and the filter inductance value L are usually very small with respect to the term E md in every realistic setup, nonlinear term are much smaller than the linear ones. Furthermore the component x ∗ d has no influence at all in averaging terms if η is constant, thanks to the fact that it is T -periodic with zero mean value. Hence it will influence the averaged system only while η is varying, and also in this case its oscillatory part will be filtered by the av eraging procedure. As a result of the pre vious steps and considerations, the linearized a veraged model for the reduced dynamics can be written as ˙ ˜ z a = ε E md [ η a − ϕ 0 ] (53) where, as mentioned, ϕ 0 is the smallest solution of equation (16). Now it is possible to design the control input η a in order to stabilize the origin of system (53), a standard PI regulator in the a veraged variables is proposed η a = − K P ˜ z a + θ ˙ θ = − ε K I ˜ z a (54) it is further to notice that the ε factor in the integral action of the controller is introduced to keep the voltage controller speed in scale with the voltage subsystem to control, thus maintaining the two-time scale behavior of the o verall system. In order to prove the asymptotic stability of the closed-loop system resulting by the interconnection of (54) and (53) consider the change of coordinates ˜ θ = θ − ϕ 0 , which results in the closed-loop error dynamics d dt  ˜ z a ˜ θ  = ε  − E md K P E md − K I 0   ˜ z a ˜ θ  (55) since ε , E md are positive, the matrix in (55) is Hurwitz for all K P > 0, K I > 0, and system (55) result asymptotically stable despite the unknown disturbance ϕ 0 . The problem with implementing the regulator (55) is that the resulting control signal is the average value of the actual control input η , thus some procedure is required to synthesize a real-world control signal whose mean value satisfies the above conditions. In the SAF specific case this problem can be solved, consider the deri vati ve of signal η a d dt η a = d dt 1 T Z t t − T η ( τ ) d τ (56) it can be re written on the left side as the dif ference ov er one period, while the right side is replaced with the deriv ativ e of η a expressed in (54); 1 T [ η ( t ) − η ( t − T ) ] = − K P ˙ ˜ z a + ˙ ˜ θ = − K P ˙ ˜ z a − ε K I ˜ z a (57) solving for η ( t ) yields η ( t ) = − T K P ˙ ˜ z a ( t ) − ε T K I ˜ z a ( t ) + η ( t − T ) (58) using (45), the deriv ativ e of the av eraged square voltage error is actually measurable, thus the abov e for - mula is implementable. Howe ver , while the interconnection between voltage subsystem and controller is stable in sense of the averaged value, a further step is required. In the incremental implementation (58) there is no more an integral action, the control input history is kept in memory for one period, still the controller provides stability for the a veraged voltage error ˜ z a . Consider no w that for the phasor variables system, a stable steady-state guarantees that all the variables have a constant average value, while being allowed to oscillate freely . This property is desired for what concern the capacitor voltage and it is the main motiv ation for applying the av eraging procedure, howe ver implementation according to (58) can introduce undesired periodic oscillation in the control input η , moreover oscillation will persist being remembered through the time delay term. In summary , while η a will approach the con- stant power loss value ϕ 0 , the actual input η might be any periodic signal with av erage value equal to ϕ 0 . Recalling that η modifies the real po wer reference v alue x ∗ d , an y oscillation will result in a non-zero error for the power tracking controller . In order to av oid this situation the following term can be added to (58) d η ( t ) = η ( t − T ) − η a ( t − T / 2 ) (59) the reason of this modification is to cancel the oscillations stored in memory , by correcting the stored signal to wards its o wn mean value η a ( t − T / 2 ) . It is important to remark that the a veraged v alue is not the actual mean value of its corresponding signal, the mean v alue s m of a signal s ( t ) is defined as s m = 1 T Z t + T / 2 t − T / 2 s ( τ ) d τ (60) the above equation is identical to the zero-order phasor definition, except for a time shift of T / 2. F or this reason the mean value of the stored signal η ( t − T ) has been expressed as its time shifted av erage value, note that the mean value of this stored signal can be computed because also its “future” values are available. The additive term d η is a zero mean value signal, because it is obtained removing its DC-value to a periodic signal. Since the control input η enters the averaged system (55) after being av eraged itself, any modification having zero mean value will not affect the behavior of the averaged system dynamics. Hence the final implementation of control input together with (59) is η ( t ) = − T K P ˙ ˜ z a − ε T K I ˜ z a + η a ( t − T / 2 ) (61) this controller will not introduce undesired oscillation because it depends solely on av eraged signals, whose simplified dynamics (55) cannot giv e oscillations. 4.2 Po wer tracking controller The voltage controller output reported in (61) can be replaced into the filter error po wer dynamics in (42), recalling also equation (54), it turns out ˙ ˜ x = M ( R , L ) ˜ x − 1 L ¯ u + d ( t ) + f ( ε , ˜ z a , ˜ θ , ˙ ˜ z a , ˙ ˜ θ ) (62) where d ( t ) = d 0 + M ( R , L ) x ∗ − ˙ x ∗ + M ( R , L ) ϕ 0 (63) is a T -periodic term composed by the sum of a constant term and sinusoids having known frequency , while f ( ˜ z a , ˜ θ , ˙ ˜ z a , ˙ ˜ θ , ε ) = T K p ¨ ˜ z a + ε K I ˙ ˜ z a + K p ˙ ˜ z a ( t − T / 2 ) − ˙ ˜ θ ( t − T / 2 ) + M ( R , L ) [ − T K p ˙ ˜ z a − ε K I ˜ z a − K p ˜ z a ( t − T / 2 ) + ˜ θ ( t − T / 2 )] . (64) The problem of forcing ˜ x in (62) clearly requires the ability of the control law to compensate for the signal d ( t ) , perfect tracking cannot be achieved by a feedforward action since SAF parameters and d ( t ) are not fully known. T o comply with uncertainties and provide robustness we propose an internal model-based controller . Each component of the vector d ( t ) can be seen as the output of the following linear system ˙ w i ( t ) = Ω w i ( t ) , w i ∈ R 2 N + 1 d im ( t ) = Γ i w i ( t ) , i = d , q (65) where Γ i ∈ R ( 1 × 2 N + 1 ) are suitably defined vectors and matrix Ω ∈ R ( 2 N + 1 ) × ( 2 N + 1 ) is defined as Ω = bl kd iag ( Ω j ) with Ω 0 = 0 and Ω j =  0 j ω m − j ω m 0  , j = 1, . . . , N (66) with the pairs ( Γ i , Ω ) observable. Defining Φ = bl k d iag ( Ω , Ω ) and Γ = bl k d iag ( Γ d , Γ q ) , the follo wing internal model-based controller can be designed ˙ ξ = Φ ξ + Q ˜ x ¯ u = Γ ξ + K ˜ x (67) where matrices Q and K need to be properly assigned. Once chosen ¯ u as in (67) and defined the internal model error variables as ˜ ξ = ξ − Lw , where w : = [ w T d , w T q ] T , the power subsystem closed-loop error dynamics can be rewritten as ˙ ˜ x = ( M ( R , L ) − 1 L K ) ˜ x − 1 L Γ ˜ ξ + f ( ˜ z a , ˜ θ , ˙ ˜ z a , ˙ ˜ θ , ε ) ˙ ˜ ξ = Φ ˜ ξ + Q ˜ x . (68) According to the general two time-scale av eraging theory , the power tracking problem can be studied focusing on the boundary layer system , obtained by putting ε = 0 into the o verall error dynamics, hence by (47), (54) and ˙ ˜ z a = 0, ˙ ˜ θ = 0, thus system (68) becomes ˙ ˜ x = ( M ( R , L ) − 1 L K ) ˜ x − 1 L Γ ˜ ξ + f ( ˜ z a , ˜ θ , 0, 0, 0 ) ˙ ˜ ξ = Φ ˜ ξ + Q ˜ x . (69) Now matrices K , Q need to be selected such that asymptotic stability is provided for the boundary layer system. Define two arbitrary Hurwitz matrices F d , F q ∈ R ( 2 N + 1 ) × ( 2 N + 1 ) , and two arbitrary vectors G d , G q such that the pairs ( F d , G d ), ( F q , G q ) are controllable, taking the controller matrices as K = k  k d 0 0 k q  , Q =  E − 1 d 0 0 E − 1 q   G d 0 0 G q  K (70) with k d , k q two arbitrary positive scalars, k a positiv e design parameter, and E d , E q defined as non- singular solutions of the following Sylv ester equations: F d E d − E d Ω d = − G d Γ d F q E q − E q Ω q = − G q Γ q (71) asymptotic stability of the boundary layer system can be stated. In order to prov e this claim let us define the vector R ξ =  − R Γ d 1 0 2 N − ω m L Γ q 1 0 2 N  T (72) where Γ d 1 , Γ q 1 denote the first element of vectors Γ d , Γ q respectiv ely and 0 2 N is a zero raw vector having dimension 2 N . Consider now the change of v ariables ˜ χ = E ˜ ξ − E R ξ ( ˜ θ ( t − T / 2 ) − K p ˜ z a ( t − T / 2 )) + LG ˜ x (73) where E = bl k d iag ( E d , E q ) , G = bl kd iag ( G d , G q ) , in this coordinates system (69) results ˙ ˜ x = ( M ( R , L ) − 1 L K + Γ L − 1 G ) ˜ x − 1 L Γ E − 1 ˜ χ ˙ ˜ χ = F ˜ χ − L ( F G − GM ( R , L ) ) ˜ x (74) where F = bl k d iag ( F d , F q ) . Using standard linear system tools it can be verified that a value ¯ k exists, such that ∀ k ≥ ¯ k the state matrix of the system in the new coordinates is Hurwitz, hence asymptotic stability of the boundary layer system can be stated. 4.3 Overall system stability Asymptotic stability has been stated for the boundary layer system and a linearized version of the av eraged reduced voltage dynamics. Exploiting the main results of the two time-scale averaged systems theory , it can be prov ed that the tw o separately designed po wer and DC-b us voltage controllers, are able to provide practical stability for the complete system (42), that is it’ s possible to claim that there exists a value ε ∗ , such that ∀ ε < ε ∗ , k ≥ ¯ k , l ≤ l ∗ the set { ( ˜ x , ˜ ξ ) : ˜ x = 0, ˜ ξ = 0 } × { ( ˜ z , ˜ θ ) : | ˜ z | ≤ l ∗ , ˜ θ = 0 } is practically stable (Khalil, 1996) for the closed-loop trajectories of the complete error system. The fact that the proposed regulator is able to achieve the control objectiv es in a practical way means that the po wer vector x can be steered arbitrary close to the reference v alue x ∗ ϕ 0 while the av eraged value η a tends arbitrary close to the power loss term ϕ 0 . It’ s further to notice that the asymptotic tracking error can be arbitrary reduced by taking a smaller value for ε , that is by increasing the capacitor value C . 5. Simulation results Simulation tests have been performed in order to validate the proposed control solution. T wo different scenarios have been adopted; first model (6) has been implemented in MA TLAB/Simulink and a load scenario with two harmonics at 7 ω m and 13 ω m has been chosen. Then, in order to validate the con- troller performance in a situation closer to a real setup, the proposed continuous-time re gulator has been discretized adopting a sampling frequency f s = 7 K H z , then the SAF conv erter components hav e been modeled by using Simulink/SimPowerSystems toolbox, and a suitable PWM technique with a carrier frequency equal to f s has been implemented. Finally a three phase diode bridge has been selected as nonlinear load scenario. The following system parameters has been set, according to the procedure illustrated in Section 3; C = 4400 µ F , L = 3.3 mH , R = 0.12 Ω , while the DC-link voltage limits have been set to v m = 700 V , v M = 900 V . Ideal three-phase mains voltages with amplitude V m = 310 V and frequency f m = 50 H z hav e been modeled. The internal-model based controller has been tuned to the load disturbances, according to the procedure described in 4.2, for what concern the simulations in time continuous domain. As regards the diode rectifier load scenario, the most relev ant power disturbances, that is the 6 t h and the 12 t h load current harmonics expressed in the synchr onous d − q reference frame (corresponding respectively to the 5 t h and the 7 t h , and to the 11 t h and the 13 t h in the fixed reference frame), ha ve been considered, then the IMC controller has been discretized according to the procedure reported in (Ronchi et al., 2003), thus the following matrices hav e been selected; Ω = bl k d iag ( Ω 0 , Ω 6 , Ω 12 ) , Γ d = Γ q = ( 1, 1, 0, 1, 0 ) T , K = d iag ( 200, 200 ) and Q = 10 3 d iag ( Q d , Q q ) , where Q d = Q q = ( 40.6, 80.7, 7.15, 78.7, 17.6 ) T . For what concerns the voltage stabilizer described in 4.1, the following parameters have been selected K P = 0.3, K I = 3.7. Consider now the performance obtained on the first simulation scenario, with ideal SAF model and the 7 t h , 13 t h disturbance harmonics; in Fig. 6 the tracking error on both real and imaginary po wer v ariables is reported, as expected, asymptotic perfect tracking is achie ved and the vector ˜ x is steered to the origin. This ideal behavior is confirmed by Fig. 7, 8; the two harmonics currents are totally canceled out by the filter currents, while a small current component oscillating at the first-order harmonic frequency and aligned to the corresponding v oltage, arises on the line side due to the v oltage controller action. In table 2 the harmonics compensation performance are summarized. Harmonic frequency [Hz] i ma [A] i l a [A] Compensation percentage 350 0.0039 10 99.96% 650 0.0038 10 99.96% T able 2. Compensation performance for the two harmonics disturbance scenario. For what concerns the voltage controller, in order to validate the stability properties, a value quite far from the mean voltage reference value ( v 2 m + v 2 M ) / 2 = 800 V has been chosen as initial condition for the capacitor voltage. As sho wed in Fig. 9, e ven though the average value is initialized at zero and needs one period before representing the actual voltage, the voltage controller reacts immediately , thanks to its dependance on the averaged deriv ative ˙ ˜ z a . Hence the voltage averaged error is successfully steered to zero, and the capacitor voltage is brought back to the middle of the safe interval, without exceeding the upper and lo wer bounds. The initial nonlinear behavior of the v oltage error trajectories is originated by the neglected nonlinearities and also by the coupling term ˜ D ( ˜ x ) , although it has been neglected due to two time-scale behavior hypothesis, it’ s excited by the internal model controller transient when harmonics compensation starts. As re gards the second simulation scenario, carried out in discrete time domain and with a more detailed filter physical model, the po wer tracking performance are reported in Fig. 10, 11, 12, in this case the power error variables ˜ x d , ˜ x q are not exactly zero, due to the fact that A C/DC rectifier high order harmonics are not compensated by the internal model, furthermore the discretization effects have to be taken into account. Howe ver the load currents harmonics for which the controller has been tuned are strongly reduced at the line side as the currents magnitude spectrum reported in Fig. 12 shows. Analyzing the currents wav eform in the time domain (Fig. 11), it can be verified that the mains currents are almost sinusoidal and perfectly aligned with the corresponding phase voltages, hence also the load imaginary po wer is almost totally compensated. The ripple introduced by the pulse with modulation can be noted on the filter current, it affects also the mains currents, howe ver thanks to a correct inductance sizing, the high frequency distortion is properly bounded. Quantitative performance of the po wer- tracking controller obtained with this scenario are summarized in T ab . 3. The current component corresponding to the line frequenc y oscillation is slightly larger at the line side than at the load side, due to the additional activ e power drained to compensate for the filter losses. As regards the av eraging voltage controller, a discrete time version has been implemented, while the same initial conditions of the first scenario hav e been reproduced. In Fig. 13 the squared voltage error , it’ s averaged value and the actual capacitor voltage are reported, also in this case the objectiv e relative to the voltage dynamics beha vior is accomplished, similar considerations to those made for the pre vious scenario can be made. Harmonic frequency [Hz] i ma [A] i l a [A] Compensation percentage 250 0.03 3.88 99.2% 350 0.04 1.91 97.9% 550 0.03 1.57 98.1% 650 0.02 1.08 98.1% T able 3. Compensation performance for the diode bridge load scenario. 1 1.025 1.05 −1000 −500 0 500 1000 time [s] [W] (a) Real power component tracking error . 1 1.025 1.05 −1000 −500 0 500 1000 time [s] [W] (b) V irtual power component tracking error . Fig. 6. Error v ariables ˜ x d , ˜ x q : two harmonics load scenario. 1 1.025 1.05 −350 −175 0 175 350 time [s] [V] 1 1.025 1.05 −25 −10 0 10 25 time [s] [A] 1 1.025 1.05 −0.5 −0.25 0 0.25 0.5 time [s] [A] 1 1.025 1.05 −25 −10 0 10 25 time [s] [A] Fig. 7. Current and line voltage w aveforms on phase a : two harmonics load scenario. 200 400 600 800 1000 0 0.005 0.01 0.015 0.02 [Hz] [A] (a) Main current magnitude spectrum. 200 400 600 800 1000 0 5 10 15 [Hz] [A] (b) Load current magnitude spectrum. Fig. 8. FFT of the a-phase main current and of the corresponding load current: two harmonics load scenario. 0 0.2 0.4 0.6 −1 −0.5 0 0.5 1 x 10 5 time [s] [V 2 ] (a) Square capacitor voltage error and com- puted av erage value (bold). 0 0.2 0.4 0.6 770 785 800 815 830 time [s] [V] (b) Actual capacitor voltage value. Fig. 9. V oltage controller performance: two harmonics load scenario. 1 1.025 1.05 −2000 −1000 0 1000 2000 time [s] [W] (a) Real power component tracking error . 1 1.025 1.05 −2000 −1000 0 1000 2000 time [s] [W] (b) V irtual power component tracking error . Fig. 10. Error v ariables ˜ x d , ˜ x q : diode bridge load scenario. 1 1.025 1.05 −350 −175 0 175 350 time [s] [V] 1 1.025 1.05 −25 −10 0 10 25 time [s] [A] 1 1.025 1.05 −25 −10 0 10 25 time [s]} [A] 1 1.025 1.05 −20 −10 0 10 20 time [s] [A] Fig. 11. Current and line voltage w aveforms on phase a : diode bridge load scenario. 0 200 400 600 800 1000 0 5 10 15 20 [Hz] [A] (a) Main current magnitude spectrum. 0 200 400 600 800 1000 0 5 10 15 20 [Hz]} [A] (b) Load current magnitude spectrum. Fig. 12. FFT of the a-phase main current and of the corresponding load current: diode bridge load scenario. 0 0.2 0.4 0.6 −1 −0.5 0 0.5 1 x 10 5 time [s] [V 2 ] (a) Square capacitor voltage error and com- puted av erage value (bold). 0 0.2 0.4 0.6 770 785 800 815 830 time [s] [V] (b) Actual capacitor voltage value. Fig. 13. V oltage controller performance: diode bridge load scenario. 6. Conclusions In this chapter a nonlinear robust control solution for a shunt active filter has been proposed, the focus has been firstly put on the hardware components design issue, providing a suitable algorithm, based on the structural system properties, which gives guarantees on the feasibility of the control problem and allows to obtain a crucial time-scale separation between the po wer and voltage dynamics. Then ex- ploiting nonlinear systems analysis well established tools, such as averaging and singular perturbation theory , an averaging capacitor voltage controller and a power tracking controller based on the internal model principle, have been presented. The former exploits the insight that, regulating the averaged voltage value, makes it possible to ignore the necessary oscillations for a proper filter operation, and improv es the voltage dynamics behavior . The second is chosen in order to ensure asymptotic tracking of undesired load current components, providing also robustness with respect to disturbances and model uncertainties. Saturation issues hav e not been explicitly addressed in this work, owing to space limitation, ho wev er it is of utmost importance to deal with these phenomena for an actual industrial implementation with sta- bility and performance guarantees. Some solutions, for the SAF specific case, hav e been proposed (see Cavini et al. (2004), Ca vini et al. (2004)), ho wev er this is still an open research topic. Future ef fort will thus be de voted to improv e the filter performance under control input saturation, analyzing the problem in the context of modern anti-windup approaches, hence providing a rigorous characterization of the system under saturation constraints. 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